Xiang Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36944 ) Change subject: arch/riscv: Fix cpu capabilities detection function ...................................................................... Patch Set 4: I read this document and made this change. Reference: https://github.com/riscv/riscv-isa-manual/blob/45e063b17f98b980efe9dd8a75a49... -- To view, visit https://review.coreboot.org/c/coreboot/+/36944 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id24f77bf21ef0c7c300faa477d67294d093eeecc Gerrit-Change-Number: 36944 Gerrit-PatchSet: 4 Gerrit-Owner: Xiang Wang <merle@hardenedlinux.org> Gerrit-Reviewer: Martin Roth <martinroth@google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com> Gerrit-Reviewer: Philipp Hug <philipp@hug.cx> Gerrit-Reviewer: Xiang Wang <merle@hardenedlinux.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org> Gerrit-Reviewer: ron minnich <rminnich@gmail.com> Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net> Gerrit-CC: Shawn C <citypw@hardenedlinux.org> Gerrit-Comment-Date: Fri, 22 Nov 2019 03:21:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment