Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5438
-gerrit
commit 8e40a8f1cc51ebea8bdcf0ce91c35224de2ad8fb Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Mon Mar 31 21:30:11 2014 +1100
superio/intel/i3100: Avoid .c includes
Following the same reasoning as commit d3043313a91dff3bc2f879ffb3b4bf23a364d711 superio/fintek/f81865f: Avoid .c includes Clean up the early_serial #include directives in mainboard/romstage code.
Change-Id: Ie74a907db8215a15e3ff282016d80b754e34d934 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/mainboard/intel/eagleheights/romstage.c | 2 +- src/mainboard/intel/mtarvon/romstage.c | 3 +-- src/mainboard/intel/truxton/romstage.c | 2 +- src/superio/intel/i3100/Makefile.inc | 2 +- src/superio/intel/i3100/early_serial.c | 3 ++- src/superio/intel/i3100/i3100.h | 4 +++- 6 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/src/mainboard/intel/eagleheights/romstage.c b/src/mainboard/intel/eagleheights/romstage.c index 3aeb71c..e2273c2 100644 --- a/src/mainboard/intel/eagleheights/romstage.c +++ b/src/mainboard/intel/eagleheights/romstage.c @@ -33,7 +33,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "southbridge/intel/i3100/reset.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "superio/smsc/smscsuperio/early_serial.c" #include "northbridge/intel/i3100/i3100.h" #include "southbridge/intel/i3100/i3100.h" diff --git a/src/mainboard/intel/mtarvon/romstage.c b/src/mainboard/intel/mtarvon/romstage.c index 0cab9bd..eb2af1b 100644 --- a/src/mainboard/intel/mtarvon/romstage.c +++ b/src/mainboard/intel/mtarvon/romstage.c @@ -29,8 +29,7 @@ #include "southbridge/intel/i3100/early_smbus.c" #include "southbridge/intel/i3100/early_lpc.c" #include "northbridge/intel/i3100/raminit.h" -#include "superio/intel/i3100/i3100.h" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" #include <spd.h> diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c index 71c5f38..7bf3a3d 100644 --- a/src/mainboard/intel/truxton/romstage.c +++ b/src/mainboard/intel/truxton/romstage.c @@ -33,7 +33,7 @@ #include "superio/intel/i3100/i3100.h" #include "cpu/x86/lapic/boot_cpu.c" #include "cpu/x86/mtrr/earlymtrr.c" -#include "superio/intel/i3100/early_serial.c" +#include <superio/intel/i3100/i3100.h> #include "cpu/x86/bist.h" #include <spd.h>
diff --git a/src/superio/intel/i3100/Makefile.inc b/src/superio/intel/i3100/Makefile.inc index bc3329e..2284398 100644 --- a/src/superio/intel/i3100/Makefile.inc +++ b/src/superio/intel/i3100/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ##
+romstage-$(CONFIG_SUPERIO_INTEL_I3100) += early_serial.c ramstage-$(CONFIG_SUPERIO_INTEL_I3100) += superio.c - diff --git a/src/superio/intel/i3100/early_serial.c b/src/superio/intel/i3100/early_serial.c index f95cf8a..ab0ad15 100644 --- a/src/superio/intel/i3100/early_serial.c +++ b/src/superio/intel/i3100/early_serial.c @@ -19,6 +19,7 @@ */
#include <arch/io.h> +#include <device/pnp.h> #include "i3100.h"
static void pnp_enter_ext_func_mode(device_t dev) @@ -45,7 +46,7 @@ static void i3100_configure_uart_clk(device_t dev, u8 predivide) pnp_exit_ext_func_mode(dev); }
-static void i3100_enable_serial(device_t dev, u16 iobase) +void i3100_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/intel/i3100/i3100.h b/src/superio/intel/i3100/i3100.h index 4b8bf27..2b9302c 100644 --- a/src/superio/intel/i3100/i3100.h +++ b/src/superio/intel/i3100/i3100.h @@ -61,4 +61,6 @@ #define I3100_UART_CLK_PREDIVIDE_8 0x01 #define I3100_UART_CLK_PREDIVIDE_26 0x02
-#endif +void i3100_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_INTEL_I3100_I3100_H */