Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32791 )
Change subject: soc/intel/cannonlake: Use CS0 for GSPI0 in FSP parameters. ......................................................................
Patch Set 3:
(1 comment)
https://review.coreboot.org/#/c/32791/3/src/soc/intel/cannonlake/fsp_params.... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/#/c/32791/3/src/soc/intel/cannonlake/fsp_params.... PS3, Line 368: params->SerialIoSpi0CsPolarity[0] = 0; : params->SerialIoSpi0CsEnable[0] = 1; Sorry, if this was not clear from my earlier comment. What I meant was: 1. Run a loop to decide if BIOS cares about a particular GSPI bus Check common_soc_config.gspi[i].speed_mhz --> where i goes from 0 to CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX
2. If speed_mhz for any bus is non-zero, set the FSP params for that bus:
a. Call gspi_get_soc_spi_cfg(i, &cfg) b. Use cfg.cs_polarity to set SerialIoSpiXCsPolarity c. Set SerialIoSpiXCsEnable[0] to 1 always because GSPI driver assumes that CS0 is used in BIOS d. Set SerialIoSpiDefaultCsOutput[i] to 0 because GSPI driver assumes that CS0 is used in BIOS.