Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/27325
Change subject: soc/amd/stoneyridge/southbridge.c: Add USB to aoac_devs table ......................................................................
soc/amd/stoneyridge/southbridge.c: Add USB to aoac_devs table
Table aoac_devs is used to define control and status registers for devices that can do D3/D0 transition (AOAC), so that there's a single delay while all devices are being enabled simultaneously. USB host are being enabled later, so that's an added delay when they are enabled. Adding USB to the table should reduce post time by some milliseconds.
BUG=b:111056662 TEST=Build and boot grunt.
Change-Id: I8dc22b3d1e1662b9ef278b18338d31fe9424f227 Signed-off-by: Richard Spiegel richard.spiegel@silverbackltd.com --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/27325/1
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 18e6c6c..ff64d9c 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -47,7 +47,9 @@ { FCH_AOAC_D3_CONTROL_I2C0, FCH_AOAC_D3_STATE_I2C0 }, { FCH_AOAC_D3_CONTROL_I2C1, FCH_AOAC_D3_STATE_I2C1 }, { FCH_AOAC_D3_CONTROL_I2C2, FCH_AOAC_D3_STATE_I2C2 }, - { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 } + { FCH_AOAC_D3_CONTROL_I2C3, FCH_AOAC_D3_STATE_I2C3 }, + { FCH_AOAC_D3_CONTROL_USB2, FCH_AOAC_D3_STATE_USB2 }, + { FCH_AOAC_D3_CONTROL_USB3, FCH_AOAC_D3_STATE_USB3 } };
static int is_sata_config(void)