Hung-Te Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36990 )
Change subject: soc/mediatek/mt8183: Use DDR clock to compute Tx delay cell ......................................................................
Patch Set 4:
(6 comments)
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@7 PS1, Line 7: Tx delay cell should use ddr clock do compute
Use DDR clock to compute Tx delay cell
Done
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 PS1, Line 9: compute
computation
Done
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 PS1, Line 9: the
The
Done
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 PS1, Line 9: using
use
Done
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@9 PS1, Line 9: ddr clock pll
DDR clock PLL
Done
https://review.coreboot.org/c/coreboot/+/36990/1//COMMIT_MSG@10 PS1, Line 10: should not div 2 more.
and should not be divided by 2.
Done