Attention is currently required from: Arthur Heymans.
Bill XIE has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/74180 )
Change subject: nb/intel/gm45: Export EDID-reading routine as a function ......................................................................
Patch Set 3:
(1 comment)
File src/northbridge/intel/gm45/gma.c:
https://review.coreboot.org/c/coreboot/+/74180/comment/57759450_150e9d87 PS3, Line 160: /* : * GTT base is at a 2M offset and is 2M big. If GTT is smaller than 2M : * cycles are simply not decoded which is fine. : */ : pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); : memset(mmio + 2 * MiB, 0, 2 * MiB);
Now it's gone?
Where should it be put?