Christian Walter has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34380 )
Change subject: src/drivers/ptt: Add PTT Support ......................................................................
src/drivers/ptt: Add PTT Support
Add Function which check if Intel Platform Trust Technology / Intel integrated TPM is enabled/active.
Change-Id: If93bb5e1a3a59b5045f4e44359683876fb387a71 Signed-off-by: Christian Walter christian.walter@9elements.com --- A src/drivers/ptt/Kconfig A src/drivers/ptt/ptt.c A src/drivers/ptt/ptt.h 3 files changed, 51 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/34380/1
diff --git a/src/drivers/ptt/Kconfig b/src/drivers/ptt/Kconfig new file mode 100644 index 0000000..b03e6d9 --- /dev/null +++ b/src/drivers/ptt/Kconfig @@ -0,0 +1,5 @@ +config INTEL_PTT + bool + default n + help + Intel Platform Trust Technology like Intel iTPM diff --git a/src/drivers/ptt/ptt.c b/src/drivers/ptt/ptt.c new file mode 100644 index 0000000..0c44942 --- /dev/null +++ b/src/drivers/ptt/ptt.c @@ -0,0 +1,37 @@ +/*. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#include <arch/early_variables.h> +#include <soc/pci_devs.h> +#include <device/pci_ops.h> + +#include "ptt.h" + +/* Dump Intel ME Register */ +static uint32_t dump_status(int index, int reg_addr) +{ + uint32_t reg = pci_read_config32(PCH_DEV_CSE, reg_addr); + + return reg; +} + +/* + * ptt_active() + * + * Check if PTT Flag is set - so that PTT is active. + * + * Return 0 if active, -1 otherwise. + */ +int ptt_active(void) +{ + // Check if PTT establishment bit is valid + uint32_t fwsts4 = dump_status(4, PCI_ME_HFSTS4); + if ((fwsts4 & PTT_ENABLE_BIT) == 0) { + printk(BIOS_DEBUG, "Intel ME Establishment Bit not valid.\n"); + return -1; + } + + return 0; +} diff --git a/src/drivers/ptt/ptt.h b/src/drivers/ptt/ptt.h new file mode 100644 index 0000000..25104d3 --- /dev/null +++ b/src/drivers/ptt/ptt.h @@ -0,0 +1,9 @@ +/*. + * Use of this source code is governed by a BSD-style license that can be + * found in the LICENSE file. + */ + +#define PCI_ME_HFSTS4 0x64 +#define PTT_ENABLE_BIT (1<<19) + +int ptt_active(void);