[coreboot-gerrit] Change in coreboot[master]: mb/google/zork: add UPDM updating function before runing FSP-M

[Martin Roth (Code Review)]

Martin Roth has submitted this change. ( https://review.coreboot.org/c/coreboot/+/51181 )

Change subject: mb/google/zork: add UPDM updating function before runing FSP-M
......................................................................

mb/google/zork: add UPDM updating function before runing FSP-M

Add the UPD updating hook in early stage for customization.

BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.

Signed-off-by: Chris Wang 
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai 
Reviewed-by: Kangheui Won 
Tested-by: build bot (Jenkins) 
---
M src/mainboard/google/zork/Makefile.inc
A src/mainboard/google/zork/romstage.c
M src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
A src/soc/amd/picasso/include/soc/romstage.h
M src/soc/amd/picasso/romstage.c
5 files changed, 29 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  EricR Lai: Looks good to me, approved
  Kangheui Won: Looks good to me, approved

diff --git a/src/mainboard/google/zork/Makefile.inc b/src/mainboard/google/zork/Makefile.inc
index 8a9d7af..4aac8f4 100644
--- a/src/mainboard/google/zork/Makefile.inc
+++ b/src/mainboard/google/zork/Makefile.inc
@@ -4,6 +4,7 @@

romstage-y += chromeos.c
 romstage-y += sku_id.c
+romstage-y += romstage.c

ramstage-y += chromeos.c
 ramstage-y += ec.c
diff --git a/src/mainboard/google/zork/romstage.c b/src/mainboard/google/zork/romstage.c
new file mode 100644
index 0000000..9ad1677
--- /dev/null
+++ b/src/mainboard/google/zork/romstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/variants.h>
+#include <soc/romstage.h>
+
+void __weak variant_updm_update(FSP_M_CONFIG *mcfg) {}
+
+void mainboard_updm_update(FSP_M_CONFIG *mcfg)
+{
+	variant_updm_update(mcfg);
+}
diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
index ac600de..230f059 100644
--- a/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/variants.h
@@ -6,6 +6,7 @@
 #include <stddef.h>
 #include <boardid.h>
 #include <ec/google/chromeec/ec.h>
+#include <FspmUpd.h>
 #include <soc/platform_descriptors.h>
 #include "chip.h"

@@ -32,6 +33,8 @@
  */
 const struct soc_amd_gpio *variant_sleep_gpio_table(size_t *size, int slp_typ);

+void variant_updm_update(FSP_M_CONFIG *mcfg);
+
 /* Program any required GPIOs at the finalize phase */
 void finalize_gpios(int slp_typ);
 /* Modify devictree settings during ramstage. */
diff --git a/src/soc/amd/picasso/include/soc/romstage.h b/src/soc/amd/picasso/include/soc/romstage.h
new file mode 100644
index 0000000..0af374f
--- /dev/null
+++ b/src/soc/amd/picasso/include/soc/romstage.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_ROMSTAGE_H_
+#define _SOC_ROMSTAGE_H_
+
+#include <fsp/api.h>
+
+void mainboard_updm_update(FSP_M_CONFIG *mcfg);
+
+#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index ecee4d3..daf2280 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -16,10 +16,12 @@
 #include <elog.h>
 #include <soc/acpi.h>
 #include <soc/pci_devs.h>
+#include <soc/romstage.h>
 #include <types.h>
 #include "chip.h"
 #include <fsp/api.h>

+void __weak mainboard_updm_update(FSP_M_CONFIG *mupd) {}
 static struct chipset_power_state chipset_state;

static void fill_chipset_state(void)
@@ -139,6 +141,8 @@
    mcfg->telemetry_vddcr_soc_offset = config->telemetry_vddcr_soc_offset;
    mcfg->hd_audio_enable = devtree_hda_dev_enabled();
    mcfg->sata_enable = devtree_sata_dev_enabled();
+
+	mainboard_updm_update(mcfg);
 }

asmlinkage void car_stage_entry(void)