[coreboot-gerrit] Change in coreboot[master]: soc/intel/common: Add function to check if PCI device is a LPSS contr...

[Aamir Bohra (Code Review)]

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/34137 )

Change subject: soc/intel/common: Add function to check if PCI device is a LPSS controller
......................................................................

soc/intel/common: Add function to check if PCI device is a LPSS controller

Change-Id: I3f5bb268fc581280bb1b87b6b175a0299a24a44a
Signed-off-by: Aamir Bohra 
---
M src/soc/intel/common/block/include/intelblocks/lpss.h
M src/soc/intel/common/block/lpss/lpss.c
2 files changed, 24 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/34137/1

diff --git a/src/soc/intel/common/block/include/intelblocks/lpss.h b/src/soc/intel/common/block/include/intelblocks/lpss.h
index eb38f13..059b06d 100644
--- a/src/soc/intel/common/block/include/intelblocks/lpss.h
+++ b/src/soc/intel/common/block/include/intelblocks/lpss.h
@@ -16,6 +16,7 @@
 #ifndef SOC_INTEL_COMMON_BLOCK_LPSS_H
 #define SOC_INTEL_COMMON_BLOCK_LPSS_H

+#include <device/device.h>
 #include <stdint.h>

/* Gets controller out of reset */
@@ -30,4 +31,7 @@
 /* Check if controller is in reset. */
 bool lpss_is_controller_in_reset(uintptr_t base);

+/* Check if the device is a LPSS controller */
+bool is_lpss(struct device *dev);
+
 #endif	/* SOC_INTEL_COMMON_BLOCK_LPSS_H */
diff --git a/src/soc/intel/common/block/lpss/lpss.c b/src/soc/intel/common/block/lpss/lpss.c
index 6b6d17b..46cd6e7 100644
--- a/src/soc/intel/common/block/lpss/lpss.c
+++ b/src/soc/intel/common/block/lpss/lpss.c
@@ -15,6 +15,7 @@

#include <device/mmio.h>
 #include <intelblocks/lpss.h>
+#include <soc/soc_chip.h>

/* Clock register */
 #define LPSS_CLOCK_CTL_REG	0x200
@@ -39,6 +40,12 @@
 /* DMA Software Reset Control */
 #define LPSS_DMA_RST_RELEASE	(1 << 2)

+/* SoC override function */
+__weak const int *soc_lpss_controllers(int *size)
+{
+	return NULL;
+}
+
 bool lpss_is_controller_in_reset(uintptr_t base)
 {
    uint8_t *addr = (void *)base;
@@ -69,3 +76,16 @@

write32(addr, clk_sel);
 }
+
+bool is_lpss(struct device *dev)
+{
+	int size = 0;
+	const int *lpss_devices = soc_lpss_controllers(&size);
+	if (!lpss_devices)
+		return false;
+	for (int i = 0; i < size; i++) {
+		if (lpss_devices[i] == dev->path.pci.devfn)
+			return true;
+	}
+	return false;
+}