Attention is currently required from: Tim Wawrzynczak, Nick Vaccaro. Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/59011 )
Change subject: mb/google,intel: Split chromeos.c files ......................................................................
Patch Set 6:
(3 comments)
File src/mainboard/google/dedede/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59011/comment/152015c0_1269958e PS6, Line 15: {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW), "EC in RW"},
depthcharge uses this data to re-read the current GPIO state if applicable (there is a `resample_at_ […]
Ack
File src/mainboard/google/eve/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59011/comment/e9d213c1_b7f81501 PS6, Line 26: CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
Yes, the `crossystem` userspace utility reads the ACPI package and then it can read the GPIOs again […]
Ah, thanks for the link. From ReadGPIO() in crosssyste_arch.c line 790_
/* Do not attempt to read GPIO that is set to -1 in ACPI */ if (controller_num == 0xFFFFFFFF) return -1;
To me that looks like CROS_GPIO_VIRTUAL ignores polarity and name, and return value is the same as if the virtual GPIO was never present in CRHW.GPIO.
File src/mainboard/google/parrot/chromeos.c:
https://review.coreboot.org/c/coreboot/+/59011/comment/eb8bcef0_8cc133df PS6, Line 25: {101, ACTIVE_LOW, (gen_pmcon_1 >> 9) & 1, "power"},
maybe the PB was wired up to the PCH as well? not sure, but it does look fishy
Literal GPIOs 100 and 101 appeared somewhere else too.