Maxim has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/83708?usp=email )
Change subject: soc/intel, pci_ids: Add Intel UHD Graphics 610 DID ......................................................................
soc/intel, pci_ids: Add Intel UHD Graphics 610 DID
https://web.archive.org/web/20240731145507/https:// linux-hardware.org/?id=pci:8086-9ba8-103c-8768
Test: $ cbmem -c * * * [DEBUG] CPU: Intel(R) Celeron(R) G5905 CPU @ 3.50GHz [DEBUG] CPU: ID a0653, Cometlake-H/S G1 (6+2), ucode: 000000f9 [DEBUG] CPU: AES supported, TXT NOT supported, VT supported [DEBUG] MCH: device id 9b73 (rev 03) is CometLake-S G0/G1 (2+2) [DEBUG] PCH: device id 0687 (rev 00) is Cometlake-H Q470 [DEBUG] IGD: device id 9ba8 (rev 03) is CometLake ULT GT1 * * *
Change-Id: Iacab0a03388af3f6fd5d78a597580037889e8ef2 Signed-off-by: Maxim Polyakov max.senia.poliak@gmail.com --- M src/include/device/pci_ids.h M src/soc/intel/cannonlake/bootblock/report_platform.c M src/soc/intel/common/block/graphics/graphics.c 3 files changed, 3 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/83708/1
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 8b2de41..fdbff82 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4174,6 +4174,7 @@ #define PCI_DID_INTEL_CML_GT2_ULT_2 0x9B4A #define PCI_DID_INTEL_CML_GT1_ULT_3 0x9B2B #define PCI_DID_INTEL_CML_GT1_ULT_4 0x9B2C +#define PCI_DID_INTEL_CML_GT1_ULT_6 0x9BA8 #define PCI_DID_INTEL_CML_GT2_ULT_5 0x9BAA #define PCI_DID_INTEL_CML_GT2_ULT_8 0x9BAC #define PCI_DID_INTEL_CML_GT2_ULT_6 0x9BCA diff --git a/src/soc/intel/cannonlake/bootblock/report_platform.c b/src/soc/intel/cannonlake/bootblock/report_platform.c index c062746..02ec8b3 100644 --- a/src/soc/intel/cannonlake/bootblock/report_platform.c +++ b/src/soc/intel/cannonlake/bootblock/report_platform.c @@ -136,6 +136,7 @@ { PCI_DID_INTEL_CML_GT2_ULT_2, "CometLake ULT GT2" }, { PCI_DID_INTEL_CML_GT1_ULT_3, "CometLake ULT GT1" }, { PCI_DID_INTEL_CML_GT1_ULT_4, "CometLake ULT GT1" }, + { PCI_DID_INTEL_CML_GT1_ULT_6, "CometLake ULT GT1" }, { PCI_DID_INTEL_CML_GT2_ULT_3, "CometLake ULT GT2" }, { PCI_DID_INTEL_CML_GT2_ULT_4, "CometLake ULT GT2" }, { PCI_DID_INTEL_CML_GT2_ULT_5, "CometLake ULT GT2" }, diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index f1e7d7e..6024cf3 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -393,6 +393,7 @@ PCI_DID_INTEL_CML_GT2_ULT_2, PCI_DID_INTEL_CML_GT1_ULT_3, PCI_DID_INTEL_CML_GT1_ULT_4, + PCI_DID_INTEL_CML_GT1_ULT_6, PCI_DID_INTEL_CML_GT2_ULT_5, PCI_DID_INTEL_CML_GT2_ULT_6, PCI_DID_INTEL_CML_GT2_ULT_7,