Attention is currently required from: Arthur Heymans, Maulik V Vaghela, Mario Scheithauer, Angel Pons, Subrata Banik, Lean Sheng Tan, Werner Zeh, Patrick Rudolph, Felix Held. Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/55367 )
Change subject: soc/intel/elkhartlake: Introduce Intel PSE ......................................................................
Patch Set 43:
(4 comments)
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55367/comment/fcbd91ee_d37f3ca7 PS2, Line 480: : params->PchPseDmaEnable[0] = PSE_Owned; : params->PchPseDmaSbInterruptEnable[0] = 0x0; : params->PchPseUartEnable[2] = PSE_Owned; : params->PchPseHsuartEnable[2] = PSE_Owned; : params->PchPseLogOutputChannel = 0x3; //Set the log output to PSE UART 2 : params->PchPseI2cEnable[2] = PSE_Owned; : params->PchPseTimedGpioEnable[0] = PSE_Owned; : params->PchPseTimedGpioEnable[1] = PSE_Owned; : params->PchPseTimedGpioPinEnable[5] = 1; : params->PchPseTimedGpioPinEnable[6] = 1; : params->PchPseTimedGpioPinAllocation[0] = 0x0; //Set to top 20 TGPIO pins : params->PchPseTimedGpioPinAllocation[1] = 0x0; //Set to top 20 TGPIO pins : : /* : * Set to predefined GPIO Pin Muxing. If the device is disabled, it : * will not be consumed by FSP. : */ : params->PchPseTgpio6PinMux = 0x8B81A203; //GPIO pin mux for GPP_T3 : params->PchPseTgpio7PinMux = 0x8B82A40B; //GPIO pin mux for GPP_T11 : params->PchPseTgpio8PinMux = 0x8B80A607; //GPIO pin mux for GPP_B7 : params->PchPseTgpio9PinMux = 0x8B80A808; //GPIO pin mux for GPP_B8 : params->PchPseTgpio10PinMux = 0x8B86AA07; //GPIO pin mux for GPP_U7 : params->PchPseTgpio11PinMux = 0x8B86AC0B; //GPIO pin mux for GPP_U11 : params->PchPseTgpio12PinMux = 0x8B86AE13; //GPIO pin mux for GPP_U19 : params->PchPseTgpio13PinMux = 0x8B85B00C; //GPIO pin mux for GPP_D12 : params->PchPseTgpio14PinMux = 0x8B90B214; //GPIO pin mux for GPP_E20 : params->PchPseTgpio15PinMux = 0x8B90B403; //GPIO pin mux for GPP_E3 : params->PchPseTgpio16PinMux = 0x8B90B607; //GPIO pin mux for GPP_E7 : params->PchPseTgpio17PinMux = 0x8B90B80F; //GPIO pin mux for GPP_E15 : params->PchPseTgpio18PinMux = 0x8B90BA06; //GPIO pin mux for GPP_E6 : params->PchPseTgpio19PinMux = 0x8B8DBC01; //GPIO pin mux for GPP_C1 : params->PchPsePwmPinMux[8] = 0x7B706604; //GPIO pin mux for GPP_E4 : params->PchPsePwmPinMux[9] = 0x7B706805; //GPIO pin mux for GPP_E5 : params->PchPsePwmPinMux[10] = 0x7B706A06; //GPIO pin mux for GPP_E6 : params->PchPsePwmPinMux[11] = 0x7B706C11; //GPIO pin mux for GPP_E17 : params->PchPsePwmPinMux[12] = 0x7B706E12; //GPIO pin mux for GPP_E18 : params->PchPsePwmPinMux[13] = 0x7B707013; //GPIO pin mux for GPP_E19 : params->PchPsePwmPinMux[14] = 0x4B64720A; //GPIO pin mux for GPP_H10 : params->PchPsePwmPinMux[15] = 0x4B64740B; //GPIO pin mux for GPP_H11 : params->PchPseSpiMosiPinMux[1] = 0x4B852003; //GPIO pin mux for GPP_D3 : params->PchPseSpiMisoPinMux[1] = 0x4B853002; //GPIO pin mux for GPP_D2 : params->PchPseSpiClkPinMux[1] = 0x4B854001; //GPIO pin mux for GPP_D1 : params->PchPseSpiCs0PinMux[1] = 0x4B855000; //GPIO pin mux for GPP_D0 : params->PchPseI2sTxPinMux[0] = 0x1B702610; //GPIO pin mux for GPP_E16 : params->PchPseI2sRxPinMux[0] = 0x1B70160F; //GPIO pin mux for GPP_E15 : params->PchPseI2sSfrmPinMux[0] = 0x1B704614; //GPIO pin mux for GPP_E21 : params->PchPseI2sSclkPinMux[0] = 0x1B703615; //GPIO pin mux for GPP_E20
Unfortunately EHL doesnt have this GpioOverride UPD. […]
What about requesting GpioOverride from the FSP team?
File src/soc/intel/elkhartlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/55367/comment/4480d0af_959e1772 PS43, Line 420: params->PchPseShellEnabled = config->PseShellEn; this should be Kconfig, not a devicetree option
https://review.coreboot.org/c/coreboot/+/55367/comment/0494f9e4_395ab6e6 PS43, Line 435: params->PchPseTimedGpioPinEnable[5] = 1; : params->PchPseTimedGpioPinEnable[6] = 1; : params->PchPseTgpio6PinMux = 0x8B81A203; : /* Set to top 20 TGPIO pins for Timed GPIO group 0 & 1 */ : params->PchPseTimedGpioPinAllocation[0] = 0x0; //Set to top 20 TGPIO pins : params->PchPseTimedGpioPinAllocation[1] = 0x0; //Set to top 20 TGPIO pins : board-specific?
https://review.coreboot.org/c/coreboot/+/55367/comment/54ced434_a17840f9 PS43, Line 427: /* Set the ownership of these devices to PSE */ : params->PchPseDmaEnable[0] = PSE_Owned; : params->PchPseUartEnable[2] = PSE_Owned; : params->PchPseHsuartEnable[2] = PSE_Owned; : params->PchPseI2cEnable[2] = PSE_Owned; : params->PchPseTimedGpioEnable[0] = PSE_Owned; : params->PchPseTimedGpioEnable[1] = PSE_Owned; : /* Enable Timed GPIO pin 5 and 6 */ : params->PchPseTimedGpioPinEnable[5] = 1; : params->PchPseTimedGpioPinEnable[6] = 1; : params->PchPseTgpio6PinMux = 0x8B81A203; : /* Set to top 20 TGPIO pins for Timed GPIO group 0 & 1 */ : params->PchPseTimedGpioPinAllocation[0] = 0x0; //Set to top 20 TGPIO pins : params->PchPseTimedGpioPinAllocation[1] = 0x0; //Set to top 20 TGPIO pins : /* Disable PSE DMA Sideband Interrupt for DMA 0 */ : params->PchPseDmaSbInterruptEnable[0] = 0x0; : /* Set the log output to PSE UART 2 */ : params->PchPseLogOutputChannel = 0x3; //Set the log output to PSE UART 2 : isn't that board-specific?