[coreboot-gerrit] Change in coreboot[master]: soc/amd/cezanne/romstage: Call preload_ramstage

[Karthik Ramasubramanian (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Marshall Dawson, Felix Held.
Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/58983 )

Change subject: soc/amd/cezanne/romstage: Call preload_ramstage
......................................................................

Patch Set 5:

(1 comment)

File src/soc/amd/cezanne/fsp_m_params.c:

https://review.coreboot.org/c/coreboot/+/58983/comment/f23f1f03_37949dcf 
PS5, Line 181: preload_ramstage();
> I was hoping the comment would explain it :( […]

Is it because cbfs_cache comes from a memory pool which can support only 2 allocations?

One is consumed by FSP-M
Other is consumed by APOB.

Only at this point, you are sure that the buffer allocated for FSP-M is freed?