Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
I think we would want to configure some of these GPIOs someday. But since ADL is not released yet, I don't mind if the definitions get added once it is.
ACK
Michael: I can't see Azalia in the GPIO group list, but looks like these pins exist in the CPU group.
EDS doesn't provide details about GPIO COMM 3 which typically has those SoC only GPIO configuration as you have asked for. From board design side, we don't expect those GPIOs would be used for any other purpose than being SoC only use. Hence COMM 3 doesn't expose those GPIO PIN in EDS. Same goes for VGPIO, JTAG, those are reserved for SOC only use and don't expect even FSP also does those programming as well.
Any GPIO with PIN MUX feature FSP has UPD to ignore FSP to program, for example: if I2C3 doesn't have device attached on board we make the UPD disable and FSP won't program the associate GPIOs hence the same GPIO can be used a general purpose (other than being NF) for other board component usage.
Depends, have a look at CNL in Linux and coreboot. HDACPU pins are in the CPU group, while AZALIA is a group on its own.
Also, I imagine the kernel doesn't have definitions for ADL GPIOs because ADL is not released yet.
Yeah, I think so, too
GPIO definition only available in EDS chapter 27 and BIOS and kernel should have same snapshot, in past i know for chromeos, folks use to refer from coreboot code to align the kernel (from ICL exp I can say so). For ADL the pin controller driver in kernel will follow the same process and ensure the sync.
Curious, are they documented elsewhere except FSP source?
EDS is the best place, FSP can program the NF and always attached with UPD, this is the process we have ensure to avoid wrong function getting programmed or FSP overrides something what CB does