Marty E. Plummer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32373 )
Change subject: rockchip: rk3399: increase memory for fit payload. ......................................................................
Patch Set 2:
Currently having an issue; was 'working' (as far as booting the embedded uImage) but now I'm stuck in coreboot land with the following:
coreboot-4.9-1422-g0987e43aa0-dirty Wed Apr 24 20:42:52 UTC 2019 bootblock starting (log level: 7)... ARM64: Exception handlers installed. PLL at 00000000ff750000: fbdiv=169, refdiv=3, postdiv1=2, postdiv2=1, vco=1352000 khz, output=676000 khz PLL at 00000000ff760080: fbdiv=99, refdiv=1, postdiv1=4, postdiv2=1, vco=2376000 khz, output=594000 khz PLL at 00000000ff760060: fbdiv=100, refdiv=1, postdiv1=3, postdiv2=1, vco=2400000 khz, output=800000 khz ADC reading 581, ID 8 PLL at 00000000ff760000: fbdiv=63, refdiv=1, postdiv1=1, postdiv2=1, vco=1512000 khz, output=1512000 khz I2C bus 0: 398584Hz (divh = 44, divl = 60) Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/romstage' CBFS: Found @ offset 80 size 6339
coreboot-4.9-1422-g0987e43aa0-dirty Wed Apr 24 20:42:52 UTC 2019 romstage starting (log level: 7)... ARM64: Exception handlers installed. ADC reading 581, ID 8 Starting DWC3 and TCPHY reset for USB OTG0 Starting DWC3 and TCPHY reset for USB OTG1 ADC reading 62, ID 0 Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'sdram-lpddr3-generic-4GB-928' CBFS: Found @ offset 710ac0 size 374 Starting SDRAM initialization... PLL at 00000000ff760040: fbdiv=116, refdiv=1, postdiv1=3, postdiv2=1, vco=2784000 khz, output=928000 khz Finish SDRAM initialization... Mapping address range [0000000000000000:00000000f8000000) as cacheable | read-write | non-secure | normal Mapping address range [0000000010000000:0000000010200000) as non-cacheable | read-write | non-secure | normal Backing address range [0000000000000000:0000000040000000) with new page table @00000000ff8e9000 CBMEM: IMD: root @ 00000000f7fff000 254 entries. IMD: root @ 00000000f7ffec00 62 entries. CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/ramstage' CBFS: Found @ offset 6400 size b761
coreboot-4.9-1422-g0987e43aa0-dirty Wed Apr 24 20:42:52 UTC 2019 ramstage starting (log level: 7)... ARM64: Exception handlers installed. BS: BS_PRE_DEVICE times (us): entry 0 run 1 exit 1 BS: BS_DEV_INIT_CHIPS times (us): entry 0 run 1 exit 1 Enumerating buses... CPU_CLUSTER: 0 enabled scan_bus: scanning of bus Root Device took 2092 usecs done BS: BS_DEV_ENUMERATE times (us): entry 1 run 9315 exit 1 Allocating resources... Reading resources... Done reading resources. Setting resources... CPU_CLUSTER: 0 missing set_resources Done setting resources. Done allocating resources. BS: BS_DEV_RESOURCES times (us): entry 1 run 16107 exit 0 Enabling resources... done. BS: BS_DEV_ENABLE times (us): entry 0 run 2620 exit 0 tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 0 ms I2C TPM 0:20 (chip type slb9645tt device-id 0x1A) TPM: Startup TPM: command 0x99 returned 0x0 TPM: Asserting physical presence TPM: command 0x4000000a returned 0x0 TPM: command 0x65 returned 0x0 TPM: flags disable=0, deactivated=0, nvlocked=1 TPM: setup succeeded Initializing devices... Root Device init ... DWC3 and TCPHY setup for USB OTG0 finished out: cmd=0x101: 03 f4 01 01 00 00 04 00 00 03 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 out: cmd=0x101: 03 f6 01 01 00 00 04 00 00 01 00 00 in-header: 03 f7 00 00 04 00 00 00 in-data: 00 00 00 02 DWC3 and TCPHY setup for USB OTG1 finished out: cmd=0x101: 03 f3 01 01 00 00 04 00 01 03 00 00 in-header: 03 f2 00 00 04 00 00 00 in-data: 00 00 01 06 out: cmd=0x101: 03 f5 01 01 00 00 04 00 01 01 00 00 in-header: 03 f2 00 00 04 00 00 00 in-data: 00 00 01 06 Root Device init finished in 74077 usecs CPU_CLUSTER: 0 init ... Attempting to set up EDP display. PLL at 00000000ff7600c0: fbdiv=337, refdiv=8, postdiv1=4, postdiv2=1, vco=1011000 khz, output=252750 khz clock recovery at voltage 0 pre-emphasis 0 requested signal parameters: lane 0 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 1 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 2 voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 3 voltage 0.4V pre_emph 3.5dB using signal parameters: voltage 0.4V pre_emph 3.5dB requested signal parameters: lane 0 voltage 0.4V pre_emph 6dB requested signal parameters: lane 1 voltage 0.4V pre_emph 6dB requested signal parameters: lane 2 voltage 0.4V pre_emph 6dB requested signal parameters: lane 3 voltage 0.4V pre_emph 6dB using signal parameters: voltage 0.4V pre_emph 6dB requested signal parameters: lane 0 voltage 0.4V pre_emph 0dB requested signal parameters: lane 1 voltage 0.4V pre_emph 0dB requested signal parameters: lane 2 voltage 0.4V pre_emph 0dB requested signal parameters: lane 3 voltage 0.4V pre_emph 0dB using signal parameters: voltage 0.4V pre_emph 0dB channel eq at voltage 0 pre-emphasis 0 PLL at 00000000ff760020: fbdiv=75, refdiv=1, postdiv1=3, postdiv2=1, vco=1800000 khz, output=600000 khz CPU_CLUSTER: 0 init finished in 126107 usecs Devices initialized BS: BS_DEV_INIT times (us): entry 63395 run 211841 exit 1 Finalize devices... Devices finalized BS: BS_POST_DEVICE times (us): entry 0 run 3488 exit 1 BS: BS_OS_RESUME_CHECK times (us): entry 1 run 1 exit 0 Writing coreboot table at 0xf7fdc000 0. 0000000000000000-00000000000fffff: BL31 1. 0000000000100000-00000000001fffff: RAMSTAGE 2. 0000000000200000-00000000002fffff: RAM 3. 0000000000300000-000000000041efff: RAMSTAGE 4. 000000000041f000-00000000f7fdbfff: RAM 5. 00000000f7fdc000-00000000f7ffffff: CONFIGURATION TABLES 6. 00000000ff3b0000-00000000ff3b1fff: BL31 7. 00000000ff8c0000-00000000ff8cffff: BL31 8. 00000000ff8e5000-00000000ff8eafff: RAMSTAGE 9. 00000000ff8ed000-00000000ff8effff: RAMSTAGE ADC reading 580, ID 8 Board ID: 8 ADC reading 62, ID 0 RAM code: 0 Manufacturer: c8 SF: Detected GD25LQ64C/GD25LB64C with sector size 0x1000, total 0x800000 CBFS: 'Master Header Locator' located CBFS at [20100:800000) FMAP: Found "FLASH" version 1.1 at 20000. FMAP: base = 0 size = 800000 #areas = 4 Wrote coreboot table at: 00000000f7fdc000, 0x1f8 bytes, checksum d5f2 coreboot table: 528 bytes. IMD ROOT 0. 00000000f7fff000 00001000 IMD SMALL 1. 00000000f7ffe000 00001000 CONSOLE 2. 00000000f7fde000 00020000 COREBOOT 3. 00000000f7fdc000 00002000 IMD small region: IMD ROOT 0. 00000000f7ffec00 00000400 BS: BS_WRITE_TABLES times (us): entry 0 run 102826 exit 1 CBFS: 'Master Header Locator' located CBFS at [20100:800000) CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1a000 size 6f6a58 Payload not loaded.