Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31435 )
Change subject: mb/ocp/monolake: fix for booting issues + tmp and ipmi support ......................................................................
Patch Set 1:
(5 comments)
Please split the commit into smaller ones: One for SMBIOS and one for the monolake.
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/Kconfig File src/mainboard/ocp/monolake/Kconfig:
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/Kconfig@1... PS1, Line 15: select MAINBOARD_HAS_TPM1 why not select the superio, too ? select SUPERIO_ITE_IT8528E why not disable the integrated soc uart ? config INTEGRATED_UART def_bool n
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl File src/mainboard/ocp/monolake/dsdt.asl:
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl@... PS1, Line 30: Name (IDTP, 0x0CA2) where are those comming from ? Is that something that can be configured in the superio ?
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl@... PS1, Line 298: Device(SPMI) Device (
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/dsdt.asl@... PS1, Line 354: Device(SYSR) Device (
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/romstage.... File src/mainboard/ocp/monolake/romstage.c:
https://review.coreboot.org/#/c/31435/1/src/mainboard/ocp/monolake/romstage.... PS1, Line 47: pci_write_config16(PCI_DEV(0, LPC_DEV, LPC_FUNC), LPC_IO_DEC, 0x0010); already done in soc code if CONFIG_INTEGRATED_UART==n