Hello build bot (Jenkins), Furquan Shaikh, Wonkyu Kim, Caveh Jalali, Roy Mingi Park, Puthikorn Voravootivat, Duncan Laurie, Tim Wawrzynczak, Subrata Banik, Nick Vaccaro, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39346
to look at the new patch set (#7).
Change subject: soc/intel/tigerlake: Add processor power limits control support ......................................................................
soc/intel/tigerlake: Add processor power limits control support
Add processor power limits control support to configure values.
BRANCH=None BUG=b:149722146 TEST=Built and checked this entry on Volteer system, cat /sys/class/powercap/intel-rapl/intel-rapl:0/*
CQ-DEPEND=CB:39345 Change-Id: I41fd95949aa2b02828aa2d13d29b962cb579904a Signed-off-by: Sumeet Pawnikar sumeet.r.pawnikar@intel.com --- A src/soc/intel/tigerlake/acpi/dptf.asl M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/fsp_params_tgl.c M src/soc/intel/tigerlake/include/soc/msr.h M src/soc/intel/tigerlake/systemagent.c 6 files changed, 261 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/39346/7