[coreboot-gerrit] Change in coreboot[master]: coreboot tables: Add PCIe info to coreboot table

[Julius Werner (Code Review)]

Attention is currently required from: Hung-Te Lin, Rex-BC Chen, Arthur Heymans, Yu-Ping Wu, Jianjun Wang.
Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63251 )

Change subject: coreboot tables: Add PCIe info to coreboot table
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Patch Set 13:

(2 comments)

File src/commonlib/include/commonlib/coreboot_tables.h:

https://review.coreboot.org/c/coreboot/+/63251/comment/f7c8d184_37b624bf 
PS12, Line 151: lb_uint64_t ctrl_base;		/* Base address of PCIe controller */
              : 	lb_uint64_t config_base;	/* Base address of Config space */
              : 	uint32_t config_size;
              : 	lb_uint64_t atu_base;
> Did you means to sort them by the variable type or length?

He means move atu_base further up so that config_size is at the end.

I don't think that's necessarily that important/useful though, since coreboot table entries themselves are only guaranteed to be 4-byte aligned. so even if the 8-byte values are aligned correctly inside the struct, there's about a 50/50 chance that the whole struct is misaligned and then they're all misaligned anyway.

File src/lib/coreboot_table.c:

https://review.coreboot.org/c/coreboot/+/63251/comment/76ed9180_b39035f9 
PS11, Line 36: CB_ERR
> I don't understand your point. […]

Yeah, sounds like a good idea to me.