Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/80005?usp=email )
Change subject: soc/intel: Unify the definition of TCO registers ......................................................................
soc/intel: Unify the definition of TCO registers
Move the definition of the TCO registers used in most boards to a separate file and use it consistently. Do not unify TCO for older incompatible platforms.
BUG=b:314260167 TEST=none
Change-Id: Id64a635d106cea879ab08aa7beca101de14b1ee6 Signed-off-by: Marek Maslanka mmaslanka@google.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/80005 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Eric Lai ericllai@google.com Reviewed-by: Jakub Czapiga czapiga@google.com --- M src/soc/intel/apollolake/elog.c M src/soc/intel/apollolake/include/soc/smbus.h M src/soc/intel/common/block/smbus/tco.c M src/soc/intel/common/block/smm/smihandler.c M src/soc/intel/common/pch/include/intelpch/smbus.h A src/soc/intel/common/tco.h M src/soc/intel/denverton_ns/include/soc/pmc.h M src/soc/intel/denverton_ns/romstage.c M src/soc/intel/xeon_sp/include/soc/smbus.h M src/southbridge/intel/common/tco.h M src/southbridge/intel/common/watchdog.c 11 files changed, 64 insertions(+), 79 deletions(-)
Approvals: build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve Jakub Czapiga: Looks good to me, approved
diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index f500b93..e5e00dd 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -76,7 +76,7 @@
/* TCO Timeout */ if (ps->prev_sleep_state != ACPI_S3 && - ps->tco1_sts & TCO_TIMEOUT) + ps->tco1_sts & TCO1_STS_TIMEOUT) elog_add_event(ELOG_TYPE_TCO_RESET);
/* Power Button Override */ diff --git a/src/soc/intel/apollolake/include/soc/smbus.h b/src/soc/intel/apollolake/include/soc/smbus.h index a87211a..067879b 100644 --- a/src/soc/intel/apollolake/include/soc/smbus.h +++ b/src/soc/intel/apollolake/include/soc/smbus.h @@ -3,19 +3,7 @@ #ifndef _SOC_APOLLOLAKE_SMBUS_H_ #define _SOC_APOLLOLAKE_SMBUS_H_
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) +#include <soc/intel/common/tco.h>
#define SMBUS_SLAVE_ADDR 0x24
diff --git a/src/soc/intel/common/block/smbus/tco.c b/src/soc/intel/common/block/smbus/tco.c index 1f1a85c..9045343 100644 --- a/src/soc/intel/common/block/smbus/tco.c +++ b/src/soc/intel/common/block/smbus/tco.c @@ -56,7 +56,7 @@
/* TCO Lock down */ tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_LOCK; + tcocnt |= TCO1_LOCK; tco_write_reg(TCO1_CNT, tcocnt); }
@@ -83,7 +83,7 @@
/* Program TCO timer halt */ tcocnt = tco_read_reg(TCO1_CNT); - tcocnt |= TCO_TMR_HLT; + tcocnt |= TCO1_TMR_HLT; tco_write_reg(TCO1_CNT, tcocnt); }
@@ -94,8 +94,8 @@
/* Make TCO issue an SMI on INTRD_DET assertion */ tcocnt = tco_read_reg(TCO2_CNT); - tcocnt &= ~TCO_INTRD_SEL_MASK; - tcocnt |= TCO_INTRD_SEL_SMI; + tcocnt &= ~TCO2_INTRD_SEL_MASK; + tcocnt |= TCO2_INTRD_SEL_SMI; tco_write_reg(TCO2_CNT, tcocnt); }
diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 6c27196..59489a4 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -460,12 +460,12 @@ if (!tco_sts) return;
- if (tco_sts & TCO_TIMEOUT) { /* TIMEOUT */ + if (tco_sts & TCO1_STS_TIMEOUT) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); }
- if (tco_sts & (TCO_INTRD_DET << 16)) { /* INTRUDER# assertion */ + if (tco_sts & (TCO2_INTRD_DET << 16)) { /* INTRUDER# assertion */ /* * Handle intrusion event * If we ever get here, probably the case has been opened. diff --git a/src/soc/intel/common/pch/include/intelpch/smbus.h b/src/soc/intel/common/pch/include/intelpch/smbus.h index 78b7953..d5501ad 100644 --- a/src/soc/intel/common/pch/include/intelpch/smbus.h +++ b/src/soc/intel/common/pch/include/intelpch/smbus.h @@ -3,19 +3,7 @@ #ifndef _INTELPCH_SMBUS_H_ #define _INTELPCH_SMBUS_H_
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) +#include <soc/intel/common/tco.h>
/* * Default slave address value for PCH. This value is set to match default diff --git a/src/soc/intel/common/tco.h b/src/soc/intel/common/tco.h new file mode 100644 index 0000000..42685cf --- /dev/null +++ b/src/soc/intel/common/tco.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _INTELPCH_TCO_H_ +#define _INTELPCH_TCO_H_ + +/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ +#define TCO_RLD 0x00 +#define TCO_DAT_IN 0x02 +#define TCO_DAT_OUT 0x03 +#define TCO1_STS 0x04 +#define TCO1_STS_TCO_SLVSEL (1 << 13) +#define TCO1_STS_CPUSERR (1 << 12) +#define TCO1_STS_CPUSMI (1 << 10) +#define TCO1_STS_CPUSCI (1 << 9) +#define TCO1_STS_BIOSWR (1 << 8) +#define TCO1_STS_NEWCENTURY (1 << 7) +#define TCO1_STS_TIMEOUT (1 << 3) +#define TCO1_STS_TCO_INT (1 << 2) +#define TCO1_STS_OS_TCO_SMI (1 << 1) +#define TCO1_STS_NMI2SMI (1 << 0) +#define TCO2_STS 0x06 +#define TCO2_STS_SMLINK_SLAVE_SMI (1 << 2) +#define TCO2_STS_SECOND_TO (1 << 1) +#define TCO2_INTRD_DET (1 << 0) +#define TCO1_CNT 0x08 +#define TCO1_LOCK (1 << 12) +#define TCO1_TMR_HLT (1 << 11) +#define TCO1_NMI2SMI_EN (1 << 9) +#define TCO1_NMI_NOW (1 << 8) +#define TCO2_CNT 0x0A +#define TCO2_OS_POLICY_MASK (3 << 4) +#define TCO2_OS_POLICY_SHUTDOWN (1 << 4) +#define TCO2_OS_POLICY_DONOT_LOAD (1 << 5) +#define TCO2_SMB_ALERT_DISABLE (1 << 3) +#define TCO2_INTRD_SEL_MASK (3 << 1) +#define TCO2_INTRD_SEL_SMI (1 << 2) +#define TCO2_INTRD_SEL_INT (1 << 1) +#define TCO_MESSAGE1 0x0C +#define TCO_MESSAGE2 0x0D +#define TCO_WDSTATUS 0x0E +#define TCO_LEGACY_ELIM 0x10 +#define TCO_IRQ12_CAUSE (1 << 1) +#define TCO_IRQ1_CAUSE (1 << 0) +#define TCO_TMR 0x12 +#define TCO_TMR_MASK 0x3FF + +#endif diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index 6e4044d..f77e4fa 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -3,6 +3,8 @@ #ifndef _DENVERTON_NS_PMC_H_ #define _DENVERTON_NS_PMC_H_
+#include <soc/intel/common/tco.h> + /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define PMC_ACPI_BASE 0x40 /* IO BAR */ #define MASK_PMC_ACPI_BASE 0xfffc @@ -214,29 +216,6 @@ #define SWGPE_EN (1 << 2) #define HOT_PLUG_EN (1 << 1)
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO_RLD 0x00 -#define TCO1_STS 0x04 -#define TCO1_STS_TCO_SLVSEL (1 << 13) -#define TCO1_STS_CPUSERR (1 << 12) -#define TCO1_STS_CPUSMI (1 << 10) -#define TCO1_STS_CPUSCI (1 << 9) -#define TCO1_STS_BIOSWR (1 << 8) -#define TCO1_STS_NEWCENTURY (1 << 7) -#define TCO1_STS_TIMEOUT (1 << 3) -#define TCO1_STS_TCO_INT (1 << 2) -#define TCO1_STS_OS_TCO_SMI (1 << 1) -#define TCO1_STS_NMI2SMI (1 << 0) -#define TCO2_STS 0x06 -#define TCO2_STS_SMLINK_SLAVE_SMI 0x04 -#define TCO2_STS_SECOND_TO 0x02 -#define TCO2_STS_INTRD_DET 0x01 -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0a -#define TCO_TMR 0x12 - /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ #define PRSTS 0x10 #define GPIO_GPE_CFG 0x120 diff --git a/src/soc/intel/denverton_ns/romstage.c b/src/soc/intel/denverton_ns/romstage.c index 2f3a5cc..8e555ef 100644 --- a/src/soc/intel/denverton_ns/romstage.c +++ b/src/soc/intel/denverton_ns/romstage.c @@ -110,7 +110,7 @@
/* Halt the TCO timer */ uint16_t reg16 = inw(tco_base + TCO1_CNT); - reg16 |= TCO_TMR_HLT; + reg16 |= TCO1_TMR_HLT; outw(reg16, tco_base + TCO1_CNT);
/* Clear the Second TCO status bit */ diff --git a/src/soc/intel/xeon_sp/include/soc/smbus.h b/src/soc/intel/xeon_sp/include/soc/smbus.h index 7ef9d0b..5d7dbb1 100644 --- a/src/soc/intel/xeon_sp/include/soc/smbus.h +++ b/src/soc/intel/xeon_sp/include/soc/smbus.h @@ -3,19 +3,7 @@ #ifndef _SOC_SMBUS_H_ #define _SOC_SMBUS_H_
-/* TCO registers and fields live behind TCOBASE I/O bar in SMBus device. */ -#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) -#define TCO_INTRD_DET (1 << 0) -#define TCO1_CNT 0x08 -#define TCO_LOCK (1 << 12) -#define TCO_TMR_HLT (1 << 11) -#define TCO2_CNT 0x0A -#define TCO_INTRD_SEL_MASK (3 << 1) -#define TCO_INTRD_SEL_SMI (1 << 2) -#define TCO_INTRD_SEL_INT (1 << 1) +#include <soc/intel/common/tco.h>
/* SMBus I/O bits. */ #define SMBUS_SLAVE_ADDR 0x24 diff --git a/src/southbridge/intel/common/tco.h b/src/southbridge/intel/common/tco.h index 5bf386f..b586fe5 100644 --- a/src/southbridge/intel/common/tco.h +++ b/src/southbridge/intel/common/tco.h @@ -10,13 +10,8 @@ #undef TCO1_CNT #endif
-#define PMBASE_TCO_OFFSET 0x60 +#include <soc/intel/common/tco.h>
-#define TCO1_STS 0x04 -#define TCO_TIMEOUT (1 << 3) -#define TCO2_STS 0x06 -#define TCO2_STS_SECOND_TO (1 << 1) -#define TCO1_CNT 0x08 -#define TCO_TMR_HLT (1 << 11) +#define PMBASE_TCO_OFFSET 0x60
#endif /* SOUTHBRIDGE_INTEL_COMMON_TCO_H */ diff --git a/src/southbridge/intel/common/watchdog.c b/src/southbridge/intel/common/watchdog.c index 1c43a0c..36b9525 100644 --- a/src/southbridge/intel/common/watchdog.c +++ b/src/southbridge/intel/common/watchdog.c @@ -27,11 +27,11 @@
/* Disable the watchdog timer. */ value = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT); - value |= TCO_TMR_HLT; + value |= TCO1_TMR_HLT; write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, value);
/* Clear TCO timeout status. */ - write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO_TIMEOUT); + write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_STS_TIMEOUT); write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, TCO2_STS_SECOND_TO);
printk(BIOS_DEBUG, "ICH-NM10-PCH: watchdog disabled\n");