Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/57228 )
Change subject: mb/intel/kblrvp: Do not use Legacy mode for UART #2 ......................................................................
mb/intel/kblrvp: Do not use Legacy mode for UART #2
All KBLRVP variants select the `INTEL_LPSS_UART_FOR_CONSOLE` Kconfig option and set `UART_FOR_CONSOLE` to `2`, so that UART #2 is used as coreboot console. However, the LPSS console driver requires the LPSS UART to be memory-mapped (and not I/O-mapped, like Super I/O UARTs).
KBLRVP variant RVP8 uses `PchSerialIoLegacyUart` for UART #2, which makes FSP-S configure UART #2 in legacy, I/O-mapped mode. This most likely results in the UART console not working after FSP-S has run.
This change updates RVP8 to use `PchSerialIoSkipInit` for UART #2, like the other KBLRVP variants do.
Change-Id: Ic5c78f5895fe1dd5e7be6ef7aec3de6940dd2475 Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/57228 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Michael Niewöhner foss@mniewoehner.de --- M src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb 1 file changed, 1 insertion(+), 1 deletion(-)
Approvals: build bot (Jenkins): Verified Michael Niewöhner: Looks good to me, approved
diff --git a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb index 00690fa..4bb00dd 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb +++ b/src/mainboard/intel/kblrvp/variants/rvp8/overridetree.cb @@ -147,7 +147,7 @@ [PchSerialIoIndexSpi1] = PchSerialIoDisabled, \ [PchSerialIoIndexUart0] = PchSerialIoPci, \ [PchSerialIoIndexUart1] = PchSerialIoDisabled, \ - [PchSerialIoIndexUart2] = PchSerialIoLegacyUart, \ + [PchSerialIoIndexUart2] = PchSerialIoSkipInit, \ }"
# PL2 override 25W
1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one.