[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE

[Jonathan Zhang (Code Review)]

Hello build bot (Jenkins), Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/43982

to look at the new patch set (#2).

Change subject: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE
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soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE

CPX-SP processor has 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.

It supports DDR4.

Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.

Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang 
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M src/soc/intel/xeon_sp/cpx/Kconfig
1 file changed, 11 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43982/2