[coreboot-gerrit] Change in coreboot[master]: mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to ...

[Nico Huber (Code Review)]

Nico Huber has submitted this change. ( https://review.coreboot.org/c/coreboot/+/29791 )

Change subject: mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to COM2
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mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to COM2

Enable COM2 port on SuperIO if UART index is 1. This change allows
to use full RS232 COM1 port for different purposes when COM2 is selected
as main port.

TEST=flash coreboot with console on COM2 and observer output with UBS-TTL
converter connected to COM2 header on PC Engines apu1

Signed-off-by: Michał Żygowski 
Change-Id: I1e72c5a43a302658f86dafd863e5a67580eae3e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29791
Tested-by: build bot (Jenkins) 
Reviewed-by: Kyösti Mälkki 
---
M src/mainboard/pcengines/apu1/bootblock.c
M src/mainboard/pcengines/apu1/romstage.c
2 files changed, 6 insertions(+), 7 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Kyösti Mälkki: Looks good to me, approved

diff --git a/src/mainboard/pcengines/apu1/bootblock.c b/src/mainboard/pcengines/apu1/bootblock.c
index 2d34cba..dc9f87d 100644
--- a/src/mainboard/pcengines/apu1/bootblock.c
+++ b/src/mainboard/pcengines/apu1/bootblock.c
@@ -17,9 +17,13 @@
 #include <superio/nuvoton/nct5104d/nct5104d.h>

#define SIO_PORT 0x2e
-#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+#define SERIAL1_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
+#define SERIAL2_DEV PNP_DEV(SIO_PORT, NCT5104D_SP2)

void bootblock_mainboard_early_init(void)
 {
-	nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	if (CONFIG_UART_FOR_CONSOLE == 1)
+		nuvoton_enable_serial(SERIAL2_DEV, CONFIG_TTYS0_BASE);
+	else if (CONFIG_UART_FOR_CONSOLE == 0)
+		nuvoton_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE);
 }
diff --git a/src/mainboard/pcengines/apu1/romstage.c b/src/mainboard/pcengines/apu1/romstage.c
index 20a6318..df91b04 100644
--- a/src/mainboard/pcengines/apu1/romstage.c
+++ b/src/mainboard/pcengines/apu1/romstage.c
@@ -17,15 +17,10 @@

#include <amdblocks/acpimmio.h>
 #include <northbridge/amd/agesa/state_machine.h>
-#include <superio/nuvoton/common/nuvoton.h>
-#include <superio/nuvoton/nct5104d/nct5104d.h>
 #include "gpio_ftns.h"
 #include <SB800.h>
 #include <sb_cimx.h>

-#define SIO_PORT 0x2e
-#define SERIAL_DEV PNP_DEV(SIO_PORT, NCT5104D_SP1)
-
 static void early_lpc_init(void)
 {
    u32 mmio_base;