Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47885 )
Change subject: soc/intel: Configure P2SB before other PCH controllers ......................................................................
soc/intel: Configure P2SB before other PCH controllers
This change updates bootblock_pch_early_init() to perform P2SB configuration before any other PCH controllers are initialized. This is done because the other controllers might perform PCR settings which requires the PCR base address to be configured. As the PCR base address configuration happens during P2SB initialization, this change moves the p2sb init calls before any other PCH controller initialization.
BUG=b:171534504
Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Signed-off-by: Furquan Shaikh furquan@google.com --- M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/cannonlake/bootblock/pch.c M src/soc/intel/elkhartlake/bootblock/pch.c M src/soc/intel/icelake/bootblock/pch.c M src/soc/intel/jasperlake/bootblock/pch.c M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/tigerlake/bootblock/pch.c 7 files changed, 48 insertions(+), 13 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/47885/1
diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index b7d2c15..bc921e3 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -65,11 +65,16 @@
void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet();
+ fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 242aa71..8ebfb3d 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -77,11 +77,16 @@
void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet();
+ fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index 9224c48..e1b7d85 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -62,11 +62,16 @@
void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet();
+ fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index f36bd31..a6b6b20 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -58,11 +58,16 @@
void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet();
+ fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index f59d9c9..96a7dc2 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -62,11 +62,16 @@
void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet();
+ fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c6b2ad9..38ae916 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -29,9 +29,14 @@
void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + + fast_spi_early_init(SPI_BASE_ADDRESS); }
static void soc_config_acpibase(void) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 18ca5e5..5c4d1d5 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -67,11 +67,16 @@
void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet();
+ fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register.