[coreboot-gerrit] Change in coreboot[master]: mainboard: herobrine: Add EC SPI and TPM macros

[Ravi kumar (Code Review)]

Ravi kumar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/56195 )

Change subject: mainboard: herobrine: Add EC SPI and TPM macros
......................................................................

mainboard: herobrine: Add EC SPI and TPM macros

Signed-off-by: Rajesh Patil 
Change-Id: Ibfc8c761ad714c3ca5201c79a5a694dd7699f9ed
---
M src/mainboard/google/herobrine/Kconfig
M src/mainboard/google/herobrine/mainboard.c
2 files changed, 8 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/56195/1

diff --git a/src/mainboard/google/herobrine/Kconfig b/src/mainboard/google/herobrine/Kconfig
index 7f88b94..a401567 100644
--- a/src/mainboard/google/herobrine/Kconfig
+++ b/src/mainboard/google/herobrine/Kconfig
@@ -45,4 +45,12 @@
    default "Senor" if BOARD_GOOGLE_SENOR
    default "Piglin" if BOARD_GOOGLE_PIGLIN

+config DRIVER_TPM_SPI_BUS
+        hex
+        default 0xE
+
+config EC_GOOGLE_CHROMEEC_SPI_BUS
+        hex
+        default 0xA
+
 endif # BOARD_GOOGLE_HEROBRINE_COMMON
diff --git a/src/mainboard/google/herobrine/mainboard.c b/src/mainboard/google/herobrine/mainboard.c
index 9f15ccb..a08b1f8 100644
--- a/src/mainboard/google/herobrine/mainboard.c
+++ b/src/mainboard/google/herobrine/mainboard.c
@@ -65,7 +65,6 @@
    qupv3_se_fw_load_and_init(QUPV3_0_SE7, SE_PROTOCOL_UART, FIFO);  /* BT UART */
    qupv3_se_fw_load_and_init(QUPV3_1_SE4, SE_PROTOCOL_SPI, MIXED);  /* ESIM SPI */
    qupv3_se_fw_load_and_init(QUPV3_1_SE5, SE_PROTOCOL_I2C, MIXED);  /* Touch I2C */
-	qupv3_se_fw_load_and_init(QUPV3_1_SE6, SE_PROTOCOL_SPI, MIXED);  /* Fingerprint SPI */

/* Set up PCIe in RC mode */
    setup_pcie();