[coreboot-gerrit] [S] Change in coreboot[main]: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache

[Subrata Banik (Code Review)]

Attention is currently required from: Andrey Petrov, Arthur Heymans, Bora Guvendik, Chen, Gang C, Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jérémy Compostella, Kapil Porwal, Paul Menzel, Ronak Kanabar, Tarun.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81212?usp=email )

Change subject: drivers/intel/fsp2_0: Support FSP-M execution from CBFS cache
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Patch Set 6:

(1 comment)

File src/drivers/intel/fsp2_0/Kconfig:

https://review.coreboot.org/c/coreboot/+/81212/comment/5d563061_096e79ee :
PS6, Line 225: Select this value when FSP-M executes from CBFS cache.
i guess the assumptions are not drafted properly about how much temp memory is required to support this feature. For example: FSP-M size is growing and what if the underlying SOC CAR doesn't have ample memory (like celeron skus) then we might see abrupt failure during boot.

Early decompression only makes sense when we have fallback memory to support with like SRAM. relying on CAR memory may not be scalable because we can't read the max CAR size and availability to choose if we wish to do XIP or copy FSP-M into temp memory and run.

Based on my understanding, this feature is better not to enable on Intel SoC unless there are some SRAM or fixed memory available.