Attention is currently required from: Arthur Heymans, Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Nico Huber, Patrick Rudolph, Tim Chu.
Shuo Liu has uploaded a new patch set (#13) to the change originally created by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/81219?usp=email )
The following approvals got outdated and were removed: Code-Review+1 by Nico Huber, Code-Review+2 by Patrick Rudolph, Verified+1 by build bot (Jenkins)
The change is no longer submittable: Code-Review and Verified are unsatisfied now.
Change subject: soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms ......................................................................
soc/intel/xeon_sp: Share DDR codes across Xeon-SP platforms
DDR support codes across generations are similar. Share the codes to improve code reuse.
TEST=intel/archercity CRB
Change-Id: I237d561003671d70dfaaa9823a0cf16d6e1f50cf Signed-off-by: Jincheng Li jincheng.li@intel.com --- M src/soc/intel/xeon_sp/Makefile.mk M src/soc/intel/xeon_sp/cpx/Makefile.mk D src/soc/intel/xeon_sp/cpx/ddr.c D src/soc/intel/xeon_sp/cpx/include/soc/ddr.h A src/soc/intel/xeon_sp/ddr.c A src/soc/intel/xeon_sp/include/soc/ddr.h M src/soc/intel/xeon_sp/spr/Makefile.mk D src/soc/intel/xeon_sp/spr/ddr.c D src/soc/intel/xeon_sp/spr/include/soc/ddr.h M src/soc/intel/xeon_sp/spr/romstage.c 10 files changed, 170 insertions(+), 300 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/81219/13