[coreboot-gerrit] [S] Change in coreboot[main]: sb/intel/bd82x6x: Use helper for PCIe hotplug

[Kyösti Mälkki (Code Review)]

Attention is currently required from: Patrick Rudolph.

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/78227?usp=email )

Change subject: sb/intel/bd82x6x: Use helper for PCIe hotplug
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Patch Set 1:

(1 comment)

File src/southbridge/intel/bd82x6x/pcie.c:

https://review.coreboot.org/c/coreboot/+/78227/comment/00d496b7_6a083c5d :
PS1, Line 213: 		pci_write_config16(dev, 0x42, 0x142);
Not in this commit, but we had a define for register 0x42 to previously set the SI Slot Implemented bit. Should this _write_ be replaced with some _update_ variant to maintain some of the other bits?

In this file registers 0x42-0x5B hit the PCI express capability block with offsets defined in PCIe specs. Readability would be largely improved using those.