Felix Held has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/32235 )
Change subject: mainboard: Add MSI MS-7707 ......................................................................
mainboard: Add MSI MS-7707
* MSI MS-7707 V1.1 (Medion OEM Akoya P4385D MSN10014555) * SandyBridge Intel P67 (BD82x6x) * Winbond 25Q32BV (4MB) * Fintek F71808A * Intel 82579V Gigabit * NEC uPD720200 USB 3.0 Host Controller * IME 7.0.4.1197
Working: * PCIe gfx adapter * PS/2 Keyboard * USB3.0 * Ethernet * S0/S3/S5 * HWM
Change-Id: I999149bb95d553ed217b2288cc34bce4fe88abb3 Signed-off-by: Max Blau tripleshiftone@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/32235 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph siro@das-labor.org --- A src/mainboard/msi/ms7707/Kconfig A src/mainboard/msi/ms7707/Kconfig.name A src/mainboard/msi/ms7707/Makefile.inc A src/mainboard/msi/ms7707/acpi/ec.asl A src/mainboard/msi/ms7707/acpi/platform.asl A src/mainboard/msi/ms7707/acpi/superio.asl A src/mainboard/msi/ms7707/acpi_tables.c A src/mainboard/msi/ms7707/board_info.txt A src/mainboard/msi/ms7707/devicetree.cb A src/mainboard/msi/ms7707/dsdt.asl A src/mainboard/msi/ms7707/gpio.c A src/mainboard/msi/ms7707/hda_verb.c A src/mainboard/msi/ms7707/romstage.c 13 files changed, 612 insertions(+), 0 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/msi/ms7707/Kconfig b/src/mainboard/msi/ms7707/Kconfig new file mode 100644 index 0000000..45ff73e --- /dev/null +++ b/src/mainboard/msi/ms7707/Kconfig @@ -0,0 +1,57 @@ +if BOARD_MSI_MS7707 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select ARCH_X86 + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select USE_NATIVE_RAMINIT + select SOUTHBRIDGE_INTEL_BD82X6X + select SUPERIO_FINTEK_F71808A + select BOARD_ROMSIZE_KB_4096 + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select MAINBOARD_USES_IFD_GBE_REGION + select NO_UART_ON_SUPERIO + select SERIRQ_CONTINUOUS_MODE + +config MAINBOARD_DIR + string + default msi/ms7707 + +config MAINBOARD_PART_NUMBER + string + default "MS-7707" + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x7707 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1462 + +config DRAM_RESET_GATE_GPIO + int + default 60 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX # FIXME: check this + int + default 2 + +config CBFS_SIZE + hex + default 0x200000 + +config VGA_BIOS_FILE + string + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vgabios.bin" + +config VGA_BIOS_ID + string + default "8086,0102" + +endif diff --git a/src/mainboard/msi/ms7707/Kconfig.name b/src/mainboard/msi/ms7707/Kconfig.name new file mode 100644 index 0000000..f6217ef --- /dev/null +++ b/src/mainboard/msi/ms7707/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_MSI_MS7707 + bool "MS-7707" diff --git a/src/mainboard/msi/ms7707/Makefile.inc b/src/mainboard/msi/ms7707/Makefile.inc new file mode 100644 index 0000000..3dae61e --- /dev/null +++ b/src/mainboard/msi/ms7707/Makefile.inc @@ -0,0 +1 @@ +romstage-y += gpio.c diff --git a/src/mainboard/msi/ms7707/acpi/ec.asl b/src/mainboard/msi/ms7707/acpi/ec.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/ms7707/acpi/ec.asl diff --git a/src/mainboard/msi/ms7707/acpi/platform.asl b/src/mainboard/msi/ms7707/acpi/platform.asl new file mode 100644 index 0000000..7c3b3c6 --- /dev/null +++ b/src/mainboard/msi/ms7707/acpi/platform.asl @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick tristan@corrick.kiwi + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} + +Method(_PTS,1) +{ +} diff --git a/src/mainboard/msi/ms7707/acpi/superio.asl b/src/mainboard/msi/ms7707/acpi/superio.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/msi/ms7707/acpi/superio.asl diff --git a/src/mainboard/msi/ms7707/acpi_tables.c b/src/mainboard/msi/ms7707/acpi_tables.c new file mode 100644 index 0000000..370b709 --- /dev/null +++ b/src/mainboard/msi/ms7707/acpi_tables.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/bd82x6x/nvs.h> + +void acpi_create_gnvs(global_nvs_t *gnvs) +{ + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + gnvs->tcrt = 100; + gnvs->tpsv = 90; +} diff --git a/src/mainboard/msi/ms7707/board_info.txt b/src/mainboard/msi/ms7707/board_info.txt new file mode 100644 index 0000000..eebec48 --- /dev/null +++ b/src/mainboard/msi/ms7707/board_info.txt @@ -0,0 +1,6 @@ +Category: desktop +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2011 diff --git a/src/mainboard/msi/ms7707/devicetree.cb b/src/mainboard/msi/ms7707/devicetree.cb new file mode 100644 index 0000000..4db2536 --- /dev/null +++ b/src/mainboard/msi/ms7707/devicetree.cb @@ -0,0 +1,117 @@ +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.link_frequency_270_mhz" = "0" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0x0 on end + device lapic 0xacac off end + end + end + device domain 0x0 on + subsystemid 0x1462 0x7707 inherit + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" + register "gen2_dec" = "0x000c0a01" + register "p_cnt_throttling_supported" = "1" + register "pcie_port_coalesce" = "1" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + register "gpe0_en" = "0x28000040" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 off end # PCIe Port #2 + device pci 1c.2 off end # PCIe Port #3 + device pci 1c.3 off end # PCIe Port #4 + device pci 1c.4 off end # PCIe Port #5 + device pci 1c.5 off end # PCIe Port #6 + device pci 1c.6 on end # PCIe Port #7 + device pci 1c.7 off end # PCIe Port #8 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge PCI-LPC bridge + chip superio/fintek/f71808a + register "multi_function_register_0" = "0x00" # 0x28 + register "multi_function_register_1" = "0xc0" # 0x29 + register "multi_function_register_2" = "0x20" # 0x2a + register "multi_function_register_3" = "0x4f" # 0x2b + register "multi_function_register_4" = "0x90" # 0x2c + register "hwm_peci_tsi_ctrl" = "0x02" # 0x0a - PECI enabled, 1.23 V + register "hwm_tcc_temp" = "0x64" # 0x0c - TCC temperature = 100 °C + register "hwm_fan1_seg1_speed" = "0xff" # 0xaa - Fan 1 segment 1 + register "hwm_fan1_seg2_speed" = "0xe2" # 0xab - Fan 1 segment 2 + register "hwm_fan1_seg3_speed" = "0xaf" # 0xac - Fan 1 segment 3 + register "hwm_fan1_seg4_speed" = "0x89" # 0xad - Fan 1 segment 4 + register "hwm_fan1_seg5_speed" = "0x72" # 0xae - Fan 1 segment 5 + register "hwm_fan1_temp_src" = "0x10" # 0xaf - Fan 1 source = PECI + register "hwm_fan2_seg1_speed" = "0xff" # 0xba - Fan 2 segment 1 = 100% + register "hwm_fan2_seg2_speed" = "0xd9" # 0xbb - Fan 2 segment 2 = 86% + register "hwm_fan2_seg3_speed" = "0xb2" # 0xbc - Fan 2 segment 3 = 74% + register "hwm_fan2_seg4_speed" = "0x99" # 0xbd - Fan 2 segment 4 = 62% + register "hwm_fan2_seg5_speed" = "0x80" # 0xbe - Fan 2 segment 5 = 50% + register "hwm_fan2_temp_src" = "0x1e" # 0xbf - Fan 2 source = temperature 2 + + register "hwm_domain1_en" = "0x01" + register "hwm_fan1_boundary_hysteresis" = "0x43" + register "hwm_vt1_boundary_1_temperature" = "0x52" # 82°C + register "hwm_vt1_boundary_2_temperature" = "0x46" # 70°C + register "hwm_vt1_boundary_3_temperature" = "0x41" # 65°C + register "hwm_vt1_boundary_4_temperature" = "0x37" # 55°C + + device pnp 4e.1 off end # Serial Port + device pnp 4e.4 on # Hardware monitor + io 0x60 = 0x295 + irq 0x70 = 0 + # global + irq 0x27 = 0x10 # PWOK follows Intel sequence + irq 0x2d = 0x2e # Anykey+MouseButton wakeup + end + device pnp 4e.5 on # Keyboard + io 0x60 = 0x060 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 4e.6 on # GPIO + irq 0x70 = 0 + irq 0xd0 = 0x20 # GPIO2 Output Enable + irq 0xd1 = 0x20 # GPIO2 Output Data + irq 0xd3 = 0x20 # GPIO2 Drive Enable + end + device pnp 4e.7 off # WDT + io 0x60 = 0xa00 + end + device pnp 4e.8 off end # CIR + device pnp 4e.a on # PME, ACPI, Power Saving Registers + irq 0xe2 = 0x0c # EuP control + irq 0xed = 0xc0 # EuP Watchdog Control + irq 0xf4 = 0x10 # Keep Last State Select + irq 0xf9 = 0x09 # LED VSB Mode Select + end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe Bridge for discrete graphics + device pci 02.0 off end # Internal graphics + end +end diff --git a/src/mainboard/msi/ms7707/dsdt.asl b/src/mainboard/msi/ms7707/dsdt.asl new file mode 100644 index 0000000..8808539 --- /dev/null +++ b/src/mainboard/msi/ms7707/dsdt.asl @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Tristan Corrick tristan@corrick.kiwi + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI 2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 // OEM revision +) +{ + /* Some generic macros */ + #include "acpi/platform.asl" + #include <cpu/intel/common/acpi/cpu.asl> + #include <southbridge/intel/bd82x6x/acpi/platform.asl> + /* global NVS and variables. */ + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> + + Device (_SB.PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <drivers/intel/gma/acpi/default_brightness_levels.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } +} diff --git a/src/mainboard/msi/ms7707/gpio.c b/src/mainboard/msi/ms7707/gpio.c new file mode 100644 index 0000000..8fd8e44 --- /dev/null +++ b/src/mainboard/msi/ms7707/gpio.c @@ -0,0 +1,189 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <southbridge/intel/common/gpio.h> + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_GPIO, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_GPIO, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_GPIO, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_GPIO, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio8 = GPIO_DIR_OUTPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio16 = GPIO_DIR_INPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio20 = GPIO_DIR_OUTPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio29 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio8 = GPIO_LEVEL_HIGH, + .gpio15 = GPIO_LEVEL_LOW, + .gpio20 = GPIO_LEVEL_HIGH, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_HIGH, + .gpio29 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = {}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = {}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_NATIVE, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_NATIVE, + .gpio51 = GPIO_MODE_NATIVE, + .gpio52 = GPIO_MODE_NATIVE, + .gpio53 = GPIO_MODE_NATIVE, + .gpio54 = GPIO_MODE_NATIVE, + .gpio55 = GPIO_MODE_NATIVE, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio57 = GPIO_DIR_OUTPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio57 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = {}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = {}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/msi/ms7707/hda_verb.c b/src/mainboard/msi/ms7707/hda_verb.c new file mode 100644 index 0000000..6a6cf41 --- /dev/null +++ b/src/mainboard/msi/ms7707/hda_verb.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0887, /* Codec Vendor / Device ID: Realtek */ + 0x14627707, /* Subsystem ID */ + + 0x0000000f, /* Number of 4 dword sets */ + /* NID 0x01: Subsystem ID. */ + AZALIA_SUBVENDOR(0x0, 0x14627707), + + /* NID 0x11. */ + AZALIA_PIN_CFG(0x0, 0x11, 0x411111f0), + + /* NID 0x12. */ + AZALIA_PIN_CFG(0x0, 0x12, 0x411111f0), + + /* NID 0x14. */ + AZALIA_PIN_CFG(0x0, 0x14, 0x01014410), + + /* NID 0x15. */ + AZALIA_PIN_CFG(0x0, 0x15, 0x01011412), + + /* NID 0x16. */ + AZALIA_PIN_CFG(0x0, 0x16, 0x01016411), + + /* NID 0x17. */ + AZALIA_PIN_CFG(0x0, 0x17, 0x01012414), + + /* NID 0x18. */ + AZALIA_PIN_CFG(0x0, 0x18, 0x01813c40), + + /* NID 0x19. */ + AZALIA_PIN_CFG(0x0, 0x19, 0x02a19c50), + + /* NID 0x1a. */ + AZALIA_PIN_CFG(0x0, 0x1a, 0x411111f0), + + /* NID 0x1b. */ + AZALIA_PIN_CFG(0x0, 0x1b, 0x02214c20), + + /* NID 0x1c. */ + AZALIA_PIN_CFG(0x0, 0x1c, 0x411111f0), + + /* NID 0x1d. */ + AZALIA_PIN_CFG(0x0, 0x1d, 0x411111f0), + + /* NID 0x1e. */ + AZALIA_PIN_CFG(0x0, 0x1e, 0x01454130), + + /* NID 0x1f. */ + AZALIA_PIN_CFG(0x0, 0x1f, 0x411111f0), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/ms7707/romstage.c b/src/mainboard/msi/ms7707/romstage.c new file mode 100644 index 0000000..30bb545 --- /dev/null +++ b/src/mainboard/msi/ms7707/romstage.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include <northbridge/intel/sandybridge/raminit_native.h> +#include <southbridge/intel/common/pmbase.h> +#include <console/console.h> +#include <southbridge/intel/bd82x6x/pch.h> + +void pch_enable_lpc(void) +{ + /* IO Decode Ranges Register */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); + /* LPC IF Enables Register (CNF2_LPC_EN|KBC_LPC_EN) */ + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x2400); + + u16 reg16; + reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4); + reg16 |= (1 << 13); // WOL Enable Override (WOL_EN_OVRD) + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0xa4, reg16); +} + +void mainboard_rcba_config(void) +{ +} + +const struct southbridge_usb_port mainboard_usb_ports[] = { + {1, 0, 0}, + {1, 0, 0}, + {1, 0, 1}, + {1, 0, 1}, + {1, 0, 2}, + {1, 0, 2}, + {1, 0, 3}, + {1, 0, 3}, + {1, 0, 4}, + {1, 0, 4}, + {1, 0, 6}, + {1, 0, 5}, + {1, 0, 5}, + {1, 0, 6}, +}; + +void mainboard_early_init(int s3resume) +{ +} + +void mainboard_config_superio(void) +{ +} + +void mainboard_get_spd(spd_raw_data *spd, bool id_only) +{ + read_spd(&spd[0], 0x50, id_only); + read_spd(&spd[2], 0x52, id_only); +}