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Hello Alok Agarwal, Anil Kumar K, Intel coreboot Reviewers, Jayvik Desai, Kapil Porwal, Pranava Y N, Subrata Banik, Vikrant L Jadeja, build bot (Jenkins),
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to look at the new patch set (#20).
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Change subject: soc/intel/pantherlake: Display Sign-of-Life during memory training ......................................................................
soc/intel/pantherlake: Display Sign-of-Life during memory training
This commit activates the Firmware Support Package (FSP) Memory Sign-of-Life feature (FSP_UGOP_EARLY_SIGN_OF_LIFE), which allows for the display of a user-configurable text message on-screen during memory initialization. This feature enhances the user experience by providing reassurance that the memory training process is underway and may take some time.
The following FSP-M UPDs (Updateable Product Data) are utilized:
- VgaInitControl (boolean): Initializes graphics, establishes VGA text mode, and centers the VgaMessage text on the screen. It clears the screen, disables VGA text mode, and deactivates graphics upon exiting the FSP-M (Firmware Support Package - Memory Initialization).
- VbtPtr (address): This is a pointer to the VBT (Video BIOS Table) binary.
- VbtSize (unsigned integer): Indicates the size of the VBT binary.
- LidStatus (boolean): Given the limited resources available at early boot stages, the text message is shown on a single monitor. The lid status determines the most appropriate display to use:
- 0: If the lid is closed, display the text message on an external display if one is available; otherwise, display nothing.
- 1: If the lid is open, display the message on the internal display; if unavailable, default to an external display.
- VgaMessage (string): Specifies the text message to be displayed.
When the FSP_UGOP_EARLY_SIGN_OF_LIFE flag is set, coreboot is configured to use the UPDs mentioned above to show a text message during the memory training phase. This text message can be customized through the locale text mechanism using the identifier memory_training_desc.
In addition, the newly introduced code records an extra event to indicate when early Sign-Of-Life has been requested, to cover the Memory Reference Code (MRC) training scenario. This event logging is crucial for debugging and analyzing the boot process, especially in production environments where it helps in pinpointing the exact stage where a boot issue might occur.
TEST="Enabling FSP-M Sign-of-Life" message is present in the log upon the first boot, and a message is displayed on the screen while the FSP performs MRC training.
Signed-off-by: Anil Kumar anil.kumar.k@intel.com Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com Change-Id: I993eb0d59cd01fa62f35a77f84e262e389efb367 --- M src/soc/intel/pantherlake/Kconfig M src/soc/intel/pantherlake/romstage/fsp_params.c 2 files changed, 37 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/85454/20