Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70112 )
Change subject: sb/intel: Use boolean for c4onc3_enable ......................................................................
sb/intel: Use boolean for c4onc3_enable
Change-Id: Ib4a5ea5f71579610721c91e8a7412da615c0d150 Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/lenovo/t400/devicetree.cb M src/mainboard/lenovo/t60/devicetree.cb M src/mainboard/lenovo/x200/devicetree.cb M src/mainboard/lenovo/x60/devicetree.cb M src/mainboard/roda/rk9/devicetree.cb M src/southbridge/intel/i82801gx/chip.h M src/southbridge/intel/i82801ix/chip.h M src/southbridge/intel/i82801jx/chip.h 9 files changed, 15 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/70112/1
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index bcce778..6b36f3e 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -56,8 +56,6 @@ register "ide_enable_primary" = "1" register "ide_enable_secondary" = "1"
- register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" register "p_cnt_throttling_supported" = "1"
diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 57f1f37..4634c71 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -64,8 +64,6 @@ register "sata_traffic_monitor" = "0"
# Set c-state support - register "c4onc3_enable" = "1" - register "c5_enable" = "1" register "c6_enable" = "1"
# Set thermal throttling to 75%. diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index dd24736..0c2ba23 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -61,7 +61,6 @@ register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000"
- register "c4onc3_enable" = "1" register "c3_latency" = "0x23" register "p_cnt_throttling_supported" = "1"
diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index 059dc00..e0eefe7 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -63,7 +63,6 @@ register "sata_traffic_monitor" = "0"
# Set c-state support - register "c4onc3_enable" = "1" register "c5_enable" = "1" register "c6_enable" = "1"
diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index f42b628..2f94328 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -54,8 +54,6 @@ register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000"
- register "c4onc3_enable" = "1" - register "c3_latency" = "0x23" register "p_cnt_throttling_supported" = "1"
diff --git a/src/mainboard/roda/rk9/devicetree.cb b/src/mainboard/roda/rk9/devicetree.cb index c9c1896..fbb026b 100644 --- a/src/mainboard/roda/rk9/devicetree.cb +++ b/src/mainboard/roda/rk9/devicetree.cb @@ -51,7 +51,6 @@ register "sata_traffic_monitor" = "0"
# Set c-state support - register "c4onc3_enable" = "0" register "c5_enable" = "1" register "c6_enable" = "1"
diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 02da70a..6711ef79 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -63,7 +63,7 @@ /* Enable linear PCIe Root Port function numbers starting at zero */ bool pcie_port_coalesce;
- int c4onc3_enable:1; + bool c4onc3_enable:true; bool docking_supported:true; int p_cnt_throttling_supported:1; int c3_latency; diff --git a/src/southbridge/intel/i82801ix/chip.h b/src/southbridge/intel/i82801ix/chip.h index ec7b977..968a81f 100644 --- a/src/southbridge/intel/i82801ix/chip.h +++ b/src/southbridge/intel/i82801ix/chip.h @@ -3,7 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801IX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801IX_CHIP_H
-#include <stdint.h> +#include <types.h>
enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, @@ -58,7 +58,7 @@ unsigned int sata_clock_request : 1; unsigned int sata_traffic_monitor : 1;
- unsigned int c4onc3_enable:1; + bool c4onc3_enable:true; unsigned int c5_enable : 1; unsigned int c6_enable : 1;
diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index ae31d4f..e36cce9 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -3,7 +3,7 @@ #ifndef SOUTHBRIDGE_INTEL_I82801JX_CHIP_H #define SOUTHBRIDGE_INTEL_I82801JX_CHIP_H
-#include <stdint.h> +#include <types.h>
enum { THTL_DEF = 0, THTL_87_5 = 1, THTL_75_0 = 2, THTL_62_5 = 3, @@ -44,7 +44,7 @@ uint8_t sata_port_map : 6; unsigned int sata_clock_request : 1;
- unsigned int c4onc3_enable:1; + bool c4onc3_enable:true; unsigned int c5_enable : 1; unsigned int c6_enable : 1;