[coreboot-gerrit] Change in ...coreboot[master]: buildsystem: Promote rules.h to default include

[Kyösti Mälkki (Code Review)]

Hello Patrick Rudolph, Aaron Durbin, Julius Werner, Paul Menzel, build bot (Jenkins), Philipp Hug, Patrick Georgi, Furquan Shaikh, ron minnich, David Guckian, Vanny E, Huang Jin, York Yang, Lee Leahy, Jonathan Neuschäfer, Nico Huber, David Guckian, Martin Roth,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/17656

to look at the new patch set (#7).

Change subject: buildsystem: Promote rules.h to default include
......................................................................

buildsystem: Promote rules.h to default include

Does not fix 3rdparty/, *.S or *.ld yet.

Change-Id: I66b48013dd89540b35ab219d2b64bc13f5f19cda
Signed-off-by: Kyösti Mälkki 
---
M Makefile.inc
M src/arch/arm64/boot.c
M src/arch/riscv/boot.c
M src/arch/riscv/stages.c
M src/arch/x86/acpi_s3.c
M src/arch/x86/exception.c
M src/arch/x86/include/arch/acpi.h
M src/arch/x86/include/arch/cpu.h
M src/arch/x86/include/arch/early_variables.h
M src/arch/x86/include/arch/exception.h
M src/arch/x86/include/arch/io.h
M src/arch/x86/include/arch/memlayout.h
M src/arch/x86/rdrand.c
M src/commonlib/storage/pci_sdhci.c
M src/console/console.c
M src/console/init.c
M src/console/post.c
M src/cpu/intel/microcode/microcode.c
M src/cpu/x86/32bit/entry32.inc
M src/cpu/x86/pae/pgtbl.c
M src/drivers/intel/fsp1_1/cache_as_ram.inc
M src/drivers/intel/fsp1_1/include/fsp/util.h
M src/drivers/intel/fsp2_0/include/fsp/info_header.h
M src/drivers/net/ne2k.c
M src/drivers/spi/spi_flash.c
M src/drivers/uart/uart8250io.c
M src/drivers/uart/uart8250mem.c
M src/include/bootstate.h
M src/include/cbmem.h
M src/include/console/cbmem_console.h
M src/include/console/console.h
M src/include/console/flash.h
M src/include/console/ne2k.h
M src/include/console/qemu_debugcon.h
M src/include/console/spi.h
M src/include/console/spkmodem.h
M src/include/console/uart.h
M src/include/console/usb.h
M src/include/device/device.h
M src/include/device/pci.h
M src/include/device/pnp.h
M src/include/memlayout.h
M src/include/stddef.h
M src/lib/bootmode.c
M src/lib/cbmem_common.c
M src/lib/ext_stage_cache.c
M src/lib/imd_cbmem.c
M src/lib/prog_loaders.c
M src/lib/romstage_handoff.c
M src/lib/timestamp.c
M src/mainboard/google/cyan/chromeos.c
M src/mainboard/google/dragonegg/chromeos.c
M src/mainboard/google/eve/chromeos.c
M src/mainboard/google/fizz/chromeos.c
M src/mainboard/google/glados/chromeos.c
M src/mainboard/google/kahlee/ec.c
M src/mainboard/google/octopus/ec.c
M src/mainboard/google/poppy/chromeos.c
M src/mainboard/google/reef/ec.c
M src/mainboard/google/sarien/chromeos.c
M src/mainboard/google/storm/mmu.c
M src/mainboard/intel/cannonlake_rvp/chromeos.c
M src/mainboard/intel/coffeelake_rvp/chromeos.c
M src/mainboard/intel/glkrvp/ec.c
M src/mainboard/intel/icelake_rvp/chromeos.c
M src/mainboard/intel/kblrvp/chromeos.c
M src/mainboard/intel/kunimitsu/chromeos.c
M src/mainboard/intel/strago/chromeos.c
M src/northbridge/intel/fsp_rangeley/northbridge.h
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/sandybridge/sandybridge.h
M src/security/vboot/bootmode.c
M src/security/vboot/vboot_common.c
M src/security/vboot/vboot_loader.c
M src/soc/amd/common/block/pi/agesawrapper.c
M src/soc/amd/stoneyridge/include/soc/pci_devs.h
M src/soc/amd/stoneyridge/include/soc/southbridge.h
M src/soc/intel/apollolake/include/soc/pci_devs.h
M src/soc/intel/apollolake/pmutil.c
M src/soc/intel/braswell/acpi.c
M src/soc/intel/braswell/include/soc/iosf.h
M src/soc/intel/braswell/include/soc/nvs.h
M src/soc/intel/braswell/include/soc/smm.h
M src/soc/intel/braswell/pmutil.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/braswell/tsc_freq.c
M src/soc/intel/cannonlake/include/soc/pci_devs.h
M src/soc/intel/cannonlake/pmutil.c
M src/soc/intel/common/block/p2sb/p2sb.c
M src/soc/intel/denverton_ns/include/soc/pci_devs.h
M src/soc/intel/icelake/include/soc/pci_devs.h
M src/soc/intel/icelake/pmutil.c
M src/soc/intel/skylake/include/soc/nvs.h
M src/soc/intel/skylake/include/soc/pch.h
M src/soc/intel/skylake/include/soc/pci_devs.h
M src/soc/intel/skylake/pmutil.c
M src/southbridge/amd/rs780/rs780.h
M src/southbridge/intel/bd82x6x/early_pch_common.c
98 files changed, 1 insertion(+), 99 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/17656/7