Nicolas Reinecke (nr@das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8307
-gerrit
commit 656e1035fd8be23c49df42079a2cc9558fb65d3e Author: Nicolas Reinecke nr@das-labor.org Date: Thu Jan 29 15:48:27 2015 +0100
southbridge/intel/bd82x6x native usb init: replace some magic values
Some magic numbers are documented in the PCH datasheet so use them.
Change-Id: I15b58ff99b3bc11ac437e5ea74f4f01b7c02032a Signed-off-by: Nicolas Reinecke nr@das-labor.org --- src/southbridge/intel/bd82x6x/early_usb_native.c | 8 ++++---- src/southbridge/intel/bd82x6x/pch.h | 6 ++++++ 2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/southbridge/intel/bd82x6x/early_usb_native.c b/src/southbridge/intel/bd82x6x/early_usb_native.c index b1f8447..b8247c6 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_native.c +++ b/src/southbridge/intel/bd82x6x/early_usb_native.c @@ -33,7 +33,7 @@ early_usb_init (const struct southbridge_usb_port *portmap) /* 3560 */ 0x024c8001, 0x000024a3, 0x00040002, 0x01000050, /* 3570 */ 0x02000772, 0x16000f9f, 0x1800ff4f, 0x0001d630, }; - const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51 , 0x2000094a, 0x2000035f }; + const u32 currents[] = { 0x20000153, 0x20000f57, 0x2000055b, 0x20000f51, 0x2000094a, 0x2000035f }; int i; /* Activate PMBAR. */ pci_write_config32(PCI_DEV(0, 0x1f, 0), PMBASE, DEFAULT_PMBASE | 1); @@ -56,17 +56,17 @@ early_usb_init (const struct southbridge_usb_port *portmap) for (i = 0; i < 14; i++) if (!portmap[i].enabled) reg32 |= (1 << i); - write32 (DEFAULT_RCBABASE | 0x359c, reg32); + write32 (DEFAULT_RCBABASE | USBPDO, reg32); reg32 = 0; for (i = 0; i < 8; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 0) reg32 |= (1 << (i + 8 * portmap[i].oc_pin)); - write32 (DEFAULT_RCBABASE | 0x35a0, reg32); + write32 (DEFAULT_RCBABASE | USBOCM1, reg32); reg32 = 0; for (i = 8; i < 14; i++) if (portmap[i].enabled && portmap[i].oc_pin >= 4) reg32 |= (1 << (i - 8 + 8 * (portmap[i].oc_pin - 4))); - write32 (DEFAULT_RCBABASE | 0x35a4, reg32); + write32 (DEFAULT_RCBABASE | USBOCM2, reg32); for (i = 0; i < 22; i++) write32 (DEFAULT_RCBABASE | (0x35a8 + 4 * i), 0);
diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7cde7bc..cfdea7c 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -438,6 +438,12 @@ early_usb_init (const struct southbridge_usb_port *portmap); #define PCH_DISABLE_MEI1 (1 << 1) #define PCH_ENABLE_DBDF (1 << 0)
+/* USB Port Disable Override */ +#define USBPDO 0x359c /* 32bit */ +/* USB Overcurrent MAP Register */ +#define USBOCM1 0x35a0 /* 32bit */ +#define USBOCM2 0x35a4 /* 32bit */ + /* ICH7 GPIOBASE */ #define GPIO_USE_SEL 0x00 #define GP_IO_SEL 0x04