Attention is currently required from: Boris Mittelberg, Caveh Jalali, Pranava Y N, Subrata Banik.
Hello Boris Mittelberg, Caveh Jalali, Pranava Y N, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85886?usp=email
to look at the new patch set (#2).
Change subject: ec/google/chromeec: Enable ACPI memory mapping for Microchip EC ......................................................................
ec/google/chromeec: Enable ACPI memory mapping for Microchip EC
This commit introduces an automatic linkage between the Microchip EC (EC_GOOGLE_CHROMEEC_MEC) and ACPI memory mapping (EC_GOOGLE_CHROMEEC_ACPI_MEMMAP) options. This linkage is enabled when the Microchip EC is selected.
Certain data registers in Microchip ECs cannot be accessed via I/O space. Instead, an indirection mechanism is required for register access. When using such an EC, coreboot must publish ACPI information to access these data registers through ACPI data ports 66h/62h.
Analysis of the coreboot codebase has revealed that the EC_GOOGLE_CHROMEEC_MEC and EC_GOOGLE_CHROMEEC_ACPI_MEMMAP options are consistently used together. This commit streamlines this dependency by linking the two options.
TEST=/sys/class/power_supply/BAT0/* reports consistent values on fatcat board.
Change-Id: Ib4120a6d0ba2f4785e8b07b33943010e58bcbdd3 Signed-off-by: Jeremy Compostella jeremy.compostella@intel.com --- M src/ec/google/chromeec/Kconfig M src/mainboard/google/cyan/Kconfig M src/mainboard/google/fatcat/Kconfig M src/mainboard/google/glados/Kconfig M src/mainboard/intel/adlrvp/Kconfig M src/mainboard/intel/kunimitsu/Kconfig M src/mainboard/intel/strago/Kconfig 7 files changed, 1 insertion(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/85886/2