[coreboot-gerrit] [S] Change in coreboot[master]: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating

[Frank Chu (Code Review)]

Frank Chu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74627 )

Change subject: mb/google/brya/marasov: Disable USB2 PHY SUS well power gating
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mb/google/brya/marasov: Disable USB2 PHY SUS well power gating

The patch disables PCH USB2 PHY power gating to prevent possible display flicker issue.
Please refer Intel doc#723158 for more information.

BUG=b:279117758
BRANCH=firmware-brya-14505.B
TEST=Verify the build for marasov board

Signed-off-by: Frank Chu 
Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72
---
M src/mainboard/google/brya/variants/marasov/overridetree.cb
1 file changed, 22 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/74627/1

diff --git a/src/mainboard/google/brya/variants/marasov/overridetree.cb b/src/mainboard/google/brya/variants/marasov/overridetree.cb
index dca4333..3b5615a 100644
--- a/src/mainboard/google/brya/variants/marasov/overridetree.cb
+++ b/src/mainboard/google/brya/variants/marasov/overridetree.cb
@@ -85,6 +85,11 @@
    	.v1p05_icc_max_ma = 500,
    	.vnn_sx_voltage_mv = 1250,
    }"
+	
+	# As per Intel Advisory doc#723158, the change is required to prevent possible
+	# display flickering issue.
+	register "usb2_phy_sus_pg_disable" = "1"	
+	
    register "serial_io_i2c_mode" = "{
    	[PchSerialIoIndexI2C0] = PchSerialIoPci,
    	[PchSerialIoIndexI2C1] = PchSerialIoPci,