[coreboot-gerrit] Change in coreboot[master]: src/mb/intel/coffeelake_rvp: Add mainboard for CML-S RVP8

[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36685 )

Change subject: src/mb/intel/coffeelake_rvp: Add mainboard for CML-S RVP8
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Patch Set 14:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36685/13/src/mainboard/intel/coffee... 
File src/mainboard/intel/coffeelake_rvp/variants/cml_s/overridetree.cb:

https://review.coreboot.org/c/coreboot/+/36685/13/src/mainboard/intel/coffee... 
PS13, Line 89: 	register "PcieRpEnable[4]" = "1"
> Yes, it is x4.

Sorry if I wasn't clear. My question is, if a PCIe root port is configured as X4, aren't the next three root port devices automatically disabled? That means only PcieRpEnable[4] would be necessary.