York Yang (york.yang@intel.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11895
-gerrit
commit c857052b97d523ce2fe47661d7e1d94b3edeade0 Author: York Yang york.yang@intel.com Date: Wed Oct 14 06:52:32 2015 -0700
intel/fsp1_0: Use dummy microcode when calling FSP TempRamInit
Pass in dummy microcode when calling FSP TempRamInit API. FSP will not do the microcode load and leave the work in coreboot. Ensure that BSP has been loaded a microcode before calling TempRamInit API, otherwise FSP will return error that No Valid Microcode Was Found.
Change-Id: I8247c0503c8eb3d1c8eaa059632fb3a11c9daae9 Signed-off-by: York Yang york.yang@intel.com --- src/drivers/intel/fsp1_0/cache_as_ram.inc | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/src/drivers/intel/fsp1_0/cache_as_ram.inc b/src/drivers/intel/fsp1_0/cache_as_ram.inc index d1167b1..5c24008 100644 --- a/src/drivers/intel/fsp1_0/cache_as_ram.inc +++ b/src/drivers/intel/fsp1_0/cache_as_ram.inc @@ -22,17 +22,12 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> -#include <microcode_size.h> #include <cbmem.h>
#ifndef CONFIG_FSP_LOC # error "CONFIG_FSP_LOC must be set." #endif
-#ifndef CONFIG_CPU_MICROCODE_CBFS_LOC -# error "CONFIG_CPU_MICROCODE_CBFS_LOC must be set." -#endif - cmp $0, %eax je cache_as_ram mov $0xa0, %eax @@ -124,11 +119,14 @@ fake_fsp_stack: .long find_fsp_ret
CAR_init_params: - .long CONFIG_CPU_MICROCODE_CBFS_LOC - .long MICROCODE_REGION_LENGTH + .long dummy_microcode + .long 0 .long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */ .long CACHE_ROM_SIZE /* Total Firmware Length */
CAR_init_stack: .long CAR_init_done .long CAR_init_params + +dummy_microcode: + .long 0