Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37976 )
Change subject: mb/bap/ode_e21XX: Switch away from ROMCC_BOOTBLOCK ......................................................................
mb/bap/ode_e21XX: Switch away from ROMCC_BOOTBLOCK
Warning: not tested on hardware.
Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: Idc7d7a632517ca211b7bb494f30851623cc625dd --- M src/mainboard/bap/ode_e21XX/Kconfig M src/mainboard/bap/ode_e21XX/Kconfig.name M src/mainboard/bap/ode_e21XX/Makefile.inc A src/mainboard/bap/ode_e21XX/bootblock.c D src/mainboard/bap/ode_e21XX/romstage.c 5 files changed, 31 insertions(+), 61 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/37976/1
diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index ff71d5b..250c74f 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -21,7 +21,6 @@ config BOARD_SPECIFIC_OPTIONS def_bool y #select BINARYPI_LEGACY_WRAPPER - #select ROMCC_BOOTBLOCK select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 select SOUTHBRIDGE_AMD_PI_AVALON diff --git a/src/mainboard/bap/ode_e21XX/Kconfig.name b/src/mainboard/bap/ode_e21XX/Kconfig.name index 64665da..5ef8804 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig.name +++ b/src/mainboard/bap/ode_e21XX/Kconfig.name @@ -1,3 +1,2 @@ -# Disabled -#config BOARD_ODE_E21XX -# bool "ODE_e21xx" +config BOARD_ODE_E21XX + bool "ODE_e21xx" diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc index b0ce627..61e474c 100644 --- a/src/mainboard/bap/ode_e21XX/Makefile.inc +++ b/src/mainboard/bap/ode_e21XX/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. #
+bootblock-y += bootblock.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c
diff --git a/src/mainboard/bap/ode_e21XX/bootblock.c b/src/mainboard/bap/ode_e21XX/bootblock.c new file mode 100644 index 0000000..8744547 --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/bootblock.c @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <amdblocks/acpimmio.h> +#include <bootblock_common.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> + +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) + +void bootblock_mainboard_early_init(void) +{ + /* Disable PCI-PCI bridge and release GPIO32/33 for other uses. */ + pm_write8(0xea, 0x1); + + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c deleted file mode 100644 index 9729ffb..0000000 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ /dev/null @@ -1,57 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <device/pci_def.h> -#include <arch/io.h> -#include <arch/cpu.h> -#include <cpu/x86/lapic.h> -#include <console/console.h> -#include <northbridge/amd/agesa/state_machine.h> -#include <southbridge/amd/pi/hudson/hudson.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f81866d/f81866d.h> - -#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) - -static void romstage_main_template(void) -{ - u32 val; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - post_code(0x31); - console_init(); - } -} - -void agesa_postcar(struct sysinfo *cb) -{ - /* After AMD_INIT_ENV -> move to ramstage ? */ - outb(0xEA, 0xCD6); - outb(0x1, 0xcd7); -}