[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Pass more SPI options to FSP.

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32791 )

Change subject: soc/intel/cannonlake: Pass more SPI options to FSP.
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Patch Set 1:

(1 comment)

These settings are just tweaking configuration int he designware ip block, no? Why are we putting in code to feed this into FSP when we already have code which configures everything?

https://review.coreboot.org/#/c/32791/1/src/soc/intel/cannonlake/chip.h 
File src/soc/intel/cannonlake/chip.h:

https://review.coreboot.org/#/c/32791/1/src/soc/intel/cannonlake/chip.h@342 
PS1, Line 342: 2
This should be based on a macro, and the bounds in the code should use ARRAY_SIZE() -- not open coding indicies and sizing.