[coreboot-gerrit] Change in coreboot[master]: nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macros

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/61400 )

Change subject: nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macros
......................................................................

nb/intel/sandybridge/raminit_mrc.c: Use <device/dram/ddr3.h> macros

Change-Id: Icca870d1c97a2737dec3f31b0f2e4c3222c711ae
Signed-off-by: Elyes HAOUAS 
---
M src/northbridge/intel/sandybridge/raminit_mrc.c
1 file changed, 13 insertions(+), 12 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/61400/1

diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c
index 4027708..8b5619c 100644
--- a/src/northbridge/intel/sandybridge/raminit_mrc.c
+++ b/src/northbridge/intel/sandybridge/raminit_mrc.c
@@ -5,6 +5,7 @@
 #include <cf9_reset.h>
 #include <string.h>
 #include <device/device.h>
+#include <device/dram/ddr3.h>
 #include <device/pci_ops.h>
 #include <arch/cpu.h>
 #include <cbmem.h>
@@ -422,14 +423,14 @@
    		dimm->dimm_num = 0;
    		dimm->bank_locator = i * 2;
    		memcpy(dimm->serial,				/* bytes 122-125 */
-				&pei_data->spd_data[0][122],
-				sizeof(uint8_t) * 4);
+				&pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
+				sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
    		memcpy(dimm->module_part_number,		/* bytes 128-145 */
-				&pei_data->spd_data[0][128],
-				sizeof(uint8_t) * 18);
+				&pei_data->spd_data[0][SPD_DIMM_PART_NUM],
+				sizeof(uint8_t) * SPD_DIMM_PART_LEN);
    		dimm->mod_id =					/* bytes 117/118 */
-				(pei_data->spd_data[0][118] << 8) |
-				(pei_data->spd_data[0][117] & 0xFF);
+				(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
+				(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
    		dimm->mod_type = DDR3_SPD_SODIMM;
    		dimm->bus_width = MEMORY_BUS_WIDTH_64;
    		dimm_cnt++;
@@ -446,14 +447,14 @@
    		dimm->dimm_num = 1;
    		dimm->bank_locator = i * 2;
    		memcpy(dimm->serial,				/* bytes 122-125 */
-				&pei_data->spd_data[0][122],
-				sizeof(uint8_t) * 4);
+				&pei_data->spd_data[0][SPD_DIMM_SERIAL_NUM],
+				sizeof(uint8_t) * SPD_DIMM_SERIAL_LEN);
    		memcpy(dimm->module_part_number,		/* bytes 128-145 */
-				&pei_data->spd_data[0][128],
-				sizeof(uint8_t) * 18);
+				&pei_data->spd_data[0][SPD_DIMM_PART_NUM],
+				sizeof(uint8_t) * SPD_DIMM_PART_LEN);
    		dimm->mod_id =					/* bytes 117/118 */
-				(pei_data->spd_data[0][118] << 8) |
-				(pei_data->spd_data[0][117] & 0xFF);
+				(pei_data->spd_data[0][SPD_DIMM_MOD_ID2] << 8) |
+				(pei_data->spd_data[0][SPD_DIMM_MOD_ID1] & 0xFF);
    		dimm->mod_type = DDR3_SPD_SODIMM;
    		dimm->bus_width = MEMORY_BUS_WIDTH_64;
    		dimm_cnt++;