[coreboot-gerrit] Change in coreboot[master]: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35014 )

Change subject: Move and rename ARCH_STAGE_HAS_xxx_SECTION rules
......................................................................

Move and rename ARCH_STAGE_HAS_xxx_SECTION rules

Currently only x86 requires special handling here, for simplicity
avoid introducing <arch/rules.h> and deal with this directly in
<rules.h>.

For consistency prefixes are changed from ARCH_ to ENV_.

The new definition of ENV_STAGE_HAS_HEAP_SECTION is changed
to reflect whether our build for the stage includes implementation
of malloc().

Change-Id: I95a56dbad3482202f6cc03043589bebfb13c39af
Signed-off-by: Kyösti Mälkki 
---
M src/arch/x86/include/arch/memlayout.h
M src/include/memlayout.h
M src/include/rules.h
M src/lib/program.ld
4 files changed, 16 insertions(+), 28 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/35014/1

diff --git a/src/arch/x86/include/arch/memlayout.h b/src/arch/x86/include/arch/memlayout.h
index de80f42..7dcdd98 100644
--- a/src/arch/x86/include/arch/memlayout.h
+++ b/src/arch/x86/include/arch/memlayout.h
@@ -16,13 +16,6 @@
 #ifndef __ARCH_MEMLAYOUT_H
 #define __ARCH_MEMLAYOUT_H

-
-#if ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE
-/* No .data or .bss sections. Cache as RAM is handled separately. */
-#define ARCH_STAGE_HAS_DATA_SECTION 0
-#define ARCH_STAGE_HAS_BSS_SECTION 0
-#endif
-
 #if (CONFIG_RAMTOP == 0)
 # error "CONFIG_RAMTOP not configured"
 #endif
diff --git a/src/include/memlayout.h b/src/include/memlayout.h
index 1ed87b6..505ccc1 100644
--- a/src/include/memlayout.h
+++ b/src/include/memlayout.h
@@ -30,24 +30,6 @@
 #define ARCH_CACHELINE_ALIGN_SIZE 64
 #endif

-/* Default to data as well as bss. */
-#ifndef ARCH_STAGE_HAS_DATA_SECTION
-#define ARCH_STAGE_HAS_DATA_SECTION 1
-#endif
-
-#ifndef ARCH_STAGE_HAS_BSS_SECTION
-#define ARCH_STAGE_HAS_BSS_SECTION 1
-#endif
-
-/*
- * Default is that currently ENV_PAYLOAD_LOADER enable stage, smm,
- * and rmodules have a heap.
- */
-#ifndef ARCH_STAGE_HAS_HEAP_SECTION
-#define ARCH_STAGE_HAS_HEAP_SECTION (ENV_PAYLOAD_LOADER || ENV_SMM || \
-		ENV_RMODULE)
-#endif
-
 #define STR(x) #x

#define ALIGN_COUNTER(align) \
diff --git a/src/include/rules.h b/src/include/rules.h
index 10cd715..3412e01 100644
--- a/src/include/rules.h
+++ b/src/include/rules.h
@@ -266,6 +266,19 @@
 #define ENV_PAYLOAD_LOADER ENV_RAMSTAGE
 #endif

+#if CONFIG(ARCH_X86) && (ENV_BOOTBLOCK || ENV_ROMSTAGE || ENV_VERSTAGE)
+/* No .data or .bss sections. Cache as RAM is handled separately. */
+#define ENV_STAGE_HAS_DATA_SECTION	0
+#define ENV_STAGE_HAS_BSS_SECTION	0
+#else
+/* Both .data nnd .bss, sometimes SRAM not DRAM. */
+#define ENV_STAGE_HAS_DATA_SECTION	1
+#define ENV_STAGE_HAS_BSS_SECTION	1
+#endif
+
+/* Currently ramstage and smm build with malloc().*/
+#define ENV_STAGE_HAS_HEAP_SECTION	(ENV_RAMSTAGE || ENV_SMM)
+
 /**
  * For pre-DRAM stages and post-CAR always build with simple device model, ie.
  * PCI, PNP and CPU functions operate without use of devicetree. The reason
diff --git a/src/lib/program.ld b/src/lib/program.ld
index 851aa75..1b30c0e 100644
--- a/src/lib/program.ld
+++ b/src/lib/program.ld
@@ -85,7 +85,7 @@
 #endif

/* Include data, bss, and heap in that order. Not defined for all stages. */
-#if ARCH_STAGE_HAS_DATA_SECTION
+#if ENV_STAGE_HAS_DATA_SECTION
 .data . : {
    . = ALIGN(ARCH_CACHELINE_ALIGN_SIZE);
    _data = .;
@@ -125,7 +125,7 @@
 }
 #endif

-#if ARCH_STAGE_HAS_BSS_SECTION
+#if ENV_STAGE_HAS_BSS_SECTION
 .bss . : {
    . = ALIGN(ARCH_POINTER_ALIGN_SIZE);
    _bss = .;
@@ -138,7 +138,7 @@
 }
 #endif

-#if ARCH_STAGE_HAS_HEAP_SECTION
+#if ENV_STAGE_HAS_HEAP_SECTION
 .heap . : {
    . = ALIGN(ARCH_POINTER_ALIGN_SIZE);
    _heap = .;