Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Pranava Y N, Subrata Banik.
Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/87061?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed: Code-Review+2 by Eric Lai, Code-Review+2 by Subrata Banik
Change subject: mb/google/brya/var/gimble: Enable RTD3 for SSD to resolve S0ix issue ......................................................................
mb/google/brya/var/gimble: Enable RTD3 for SSD to resolve S0ix issue
Some SSDs block the CPU from reaching C10 during the S0ix suspend without the RTD3 configuration. Add PCIe RTD3 support so NVMe gets placed into D3 state when entering S0ix.
Enable and reset GPIOs are configured as per pin mapping in gpio.c.
BUG=b:391612392 TEST=Run suspend_stress_test on gimble device and verify that the device suspends to S0ix.
Change-Id: Iac9eb63639cbb0c7708d5b2bb30aca20e09db3e7 Signed-off-by: Pranava Y N pranavayn@google.com --- M src/mainboard/google/brya/variants/gimble/overridetree.cb 1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/87061/2