[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Speed up postcar loading using intermediate cac...

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34791 )

Change subject: soc/intel/cannonlake: Speed up postcar loading using intermediate caching
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Patch Set 9:

(1 comment)

RFC CB:34897

I did not even try to make it pass builds yet.

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
File src/soc/intel/cannonlake/romstage/romstage.c:

https://review.coreboot.org/c/coreboot/+/34791/9/src/soc/intel/cannonlake/ro... 
PS9, Line 167: 	/* Cache the ROM as WP just below 4GiB. */
You do not setup TSEG cache here in the original code? That's where your ramstage will be copied before the jump, see run_ramstage(). Unless you have NO_STAGE_CACHE=y in your config.

Maybe I missed something? That would totally have messed up any performance numbers you have gathered so far.