[coreboot-gerrit] [S] Change in coreboot[main]: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs

[Vince Liu (Code Review)]

Vince Liu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/86538?usp=email )

Change subject: soc/mediatek/mt8189: Reduce bootblock size by separating SPI NOR GPIOs
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Patch Set 4:

(1 comment)

Commit Message:

https://review.coreboot.org/c/coreboot/+/86538/comment/b42c1d1a_5d97381a?usp... :
PS4, Line 9: In the bootblock stage, only SPI NOR related GPIOs are used. To optimize the code size, separate the SPI NOR GPIO driving information. This modification reduces the bootblock code size by 1KB.
> Line too long...

I guess the issue might be caused by me directly modifying in the Gerrit editor...
How should I fix this problem?