Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31596 )
Change subject: soc/intel/skylake: Unify serial IRQ options
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Patch Set 2:
(1 comment)
https://review.coreboot.org/#/c/31596/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/#/c/31596/2//COMMIT_MSG@20
PS2, Line 20: A lot of Google boards have serial IRQ enabled, while the pin
: seems to be unconnected?
It's not like you're having your schematics online, do you? ;) […]
Ah yes, all those are boards with eSPI which uses virtual wires for SERIRQ# instead of the physical line. So, yes, I am not sure if the LPC configuration register even applies or makes any difference for eSPI.
At first glance, it seems like this is a case of copy paste :) But I will let some one from Intel confirm this. +Subrata, +Rizwan.
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