[coreboot-gerrit] [M] Change in coreboot[main]: tree: Use boolean for s3resume

[Elyes Haouas (Code Review)]

Attention is currently required from: Alexander Couzens, Angel Pons, Elyes Haouas, Felix Held, Intel coreboot Reviewers, Julius Werner, Matt DeVillier.

Hello Alexander Couzens, Angel Pons, Felix Held, Intel coreboot Reviewers, Julius Werner, Matt DeVillier, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/86331?usp=email

to look at the new patch set (#4).

Change subject: tree: Use boolean for s3resume
......................................................................

tree: Use boolean for s3resume

Change-Id: I3e23134f879fcaf817cf62b641e9b59563eb643b
Signed-off-by: Elyes Haouas 
---
M src/arch/arm64/include/arch/acpi.h
M src/drivers/amd/agesa/mtrr_fixme.c
M src/drivers/tpm/tpm.c
M src/include/acpi/acpi.h
M src/include/cbmem.h
M src/include/romstage_handoff.h
M src/include/stage_cache.h
M src/lib/bootblock.c
M src/lib/imd_cbmem.c
M src/lib/romstage_handoff.c
M src/mainboard/dell/snb_ivb_workstations/romstage.c
M src/mainboard/emulation/qemu-i440fx/romstage.c
M src/mainboard/emulation/qemu-q35/romstage.c
M src/mainboard/google/auron/ec.c
M src/mainboard/google/auron/variants/gandof/variant.c
M src/mainboard/google/auron/variants/lulu/variant.c
M src/mainboard/google/auron/variants/samus/variant.c
M src/mainboard/google/link/early_init.c
M src/mainboard/google/slippy/ec.c
M src/mainboard/google/stout/early_init.c
M src/mainboard/kontron/ktqm77/early_init.c
M src/mainboard/lenovo/t420/early_init.c
M src/mainboard/lenovo/t420s/early_init.c
M src/mainboard/lenovo/t430/early_init.c
M src/mainboard/lenovo/t430s/variants/t430s/romstage.c
M src/mainboard/lenovo/t520/early_init.c
M src/mainboard/lenovo/t530/early_init.c
M src/mainboard/supermicro/x9scl/early_init.c
M src/northbridge/amd/agesa/agesa_helper.h
M src/northbridge/amd/agesa/state_machine.h
M src/northbridge/intel/e7505/romstage.c
M src/northbridge/intel/gm45/gm45.h
M src/northbridge/intel/gm45/raminit.c
M src/northbridge/intel/gm45/raminit_read_write_training.c
M src/northbridge/intel/gm45/romstage.c
M src/northbridge/intel/haswell/broadwell_mrc/raminit.c
M src/northbridge/intel/haswell/haswell_mrc/raminit.c
M src/northbridge/intel/haswell/native_raminit/raminit_native.c
M src/northbridge/intel/haswell/raminit.h
M src/northbridge/intel/haswell/romstage.c
M src/northbridge/intel/i440bx/raminit.c
M src/northbridge/intel/i440bx/raminit.h
M src/northbridge/intel/i945/early_init.c
M src/northbridge/intel/i945/i945.h
M src/northbridge/intel/i945/romstage.c
M src/northbridge/intel/ironlake/quickpath.c
M src/northbridge/intel/ironlake/raminit.c
M src/northbridge/intel/ironlake/raminit.h
M src/northbridge/intel/ironlake/romstage.c
M src/northbridge/intel/pineview/romstage.c
M src/northbridge/intel/sandybridge/raminit.c
M src/northbridge/intel/sandybridge/raminit_common.h
M src/northbridge/intel/sandybridge/raminit_mrc.c
M src/northbridge/intel/sandybridge/raminit_native.c
M src/northbridge/intel/sandybridge/romstage.c
M src/northbridge/intel/sandybridge/sandybridge.h
M src/northbridge/intel/x4x/raminit.c
M src/northbridge/via/cx700/romstage.c
M src/security/intel/txt/ramstage.c
M src/soc/amd/stoneyridge/romstage.c
M src/soc/intel/baytrail/romstage/raminit.c
M src/soc/intel/baytrail/romstage/romstage.c
M src/soc/intel/broadwell/include/soc/romstage.h
M src/soc/intel/broadwell/raminit.c
M src/soc/intel/broadwell/romstage.c
M src/southbridge/intel/lynxpoint/early_pch_native.c
M src/southbridge/intel/lynxpoint/pch.h
67 files changed, 102 insertions(+), 94 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/86331/4