Attention is currently required from: Eric Lai, Ivy Jian, Nick Vaccaro, Paul Menzel.
Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/80300?usp=email )
Change subject: mb/google/brox: Initialize TCHSCR_RST_L to 0 ......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80300/comment/496f2314_c6a231e9 : PS4, Line 10: was causing some leakage
Was it measured?
Yes it was.
https://review.coreboot.org/c/coreboot/+/80300/comment/a1c51525_90159227 : PS4, Line 10: Configuring it to 0 initially in : romstage should fix this.
s/should fix/fixes/ […]
Done
https://review.coreboot.org/c/coreboot/+/80300/comment/6d2af1ed_9464f8c0 : PS4, Line 11: Also, make sure that EN_PP3300_TCHSCR is : initialized in romstage as well.
Why?
Because if the reset value is initialized the enable value should be initialized to a proper value.
https://review.coreboot.org/c/coreboot/+/80300/comment/76ee5287_7c955daa : PS4, Line 13:
What does the schematic say?
I do not understand what you are referring to. What does the schematic say about what?
Patchset:
PS4:
This is from our HW engineer (Charlie Costakis): "My understanding is that PLT_RST_L is actually the […]
Marking resolved unless there is still something in question?