[coreboot-gerrit] [L] Change in coreboot[main]: haswell NRI: Add DDR3 JEDEC reset and init

[Alicja Michalska (Code Review)]

Attention is currently required from: Angel Pons, Arthur Heymans, Nico Huber.

Alicja Michalska has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/64189?usp=email )

Change subject: haswell NRI: Add DDR3 JEDEC reset and init
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Patch Set 8:

(4 comments)

File src/northbridge/intel/haswell/native_raminit/raminit_native.h:

https://review.coreboot.org/c/coreboot/+/64189/comment/4f35b679_fcbf84ad?usp... :
PS8, Line 79: 	RAMINIT_STATUS_UNSPECIFIED_ERROR, /** TODO: Deprecated in favor of specific values **/
Assuming error code reporting isn't ready yet?

https://review.coreboot.org/c/coreboot/+/64189/comment/b1f5d572_f4e50401?usp... :
PS8, Line 176: 	int8_t  rxvref[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES];
uint?

https://review.coreboot.org/c/coreboot/+/64189/comment/c3b1242d_bec0922f?usp... :
PS8, Line 231: /* Number of ticks to wait in units of 69.841279 ns (citation needed) */
:D

File src/southbridge/intel/lynxpoint/pch.h:

https://review.coreboot.org/c/coreboot/+/64189/comment/8d59e161_ed87707d?usp... :
PS8, Line 590: #define  PM_CFG2_DRAM_RESET_CTL	(1 << 26)	/* ULT only */
NIT: Remove the space to make it look a bit nicer?