[coreboot-gerrit] Change in coreboot[master]: nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/49535 )

Change subject: nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>
......................................................................

nb/intel/gm45/bootblock.c: include <arch/pci_io_cfg.h>

Also rename 'reg' to 'reg32'.

Change-Id: Id741f636162a8a228bca069637993422deb5e09c
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49535
Tested-by: build bot (Jenkins) 
Reviewed-by: Angel Pons 
---
M src/northbridge/intel/gm45/bootblock.c
1 file changed, 3 insertions(+), 3 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/northbridge/intel/gm45/bootblock.c b/src/northbridge/intel/gm45/bootblock.c
index 9c45f7e..e2cabdb 100644
--- a/src/northbridge/intel/gm45/bootblock.c
+++ b/src/northbridge/intel/gm45/bootblock.c
@@ -1,8 +1,8 @@
 /* SPDX-License-Identifier: GPL-2.0-only */

#include <arch/bootblock.h>
+#include <arch/pci_io_cfg.h>
 #include <assert.h>
-#include <device/pci_ops.h>
 #include <types.h>

#include "gm45.h"
@@ -31,7 +31,7 @@
     * The PCIEXBAR is assumed to live in the memory mapped IO space under
     * 4GiB.
     */
-	const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
+	const uint32_t reg32 = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
    pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_HI, 0);
-	pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg);
+	pci_io_write_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO, reg32);
 }