[coreboot-gerrit] Change in coreboot[master]: mainboard/google/volteer: Enable long cr50 ready pulses

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44359 )

Change subject: mainboard/google/volteer: Enable long cr50 ready pulses
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Patch Set 10:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44359/10/src/mainboard/google/volte... 
File src/mainboard/google/volteer/mainboard.c:

https://review.coreboot.org/c/coreboot/+/44359/10/src/mainboard/google/volte... 
PS10, Line 37: 		cfg->LpmStateDisableMask = LPM_S0i3_4;
> I have not heard the Intel engineers mention anything besides the Lpm bit7 being cleared, as necessa […]

Ideally if u have implemented long TPM IRQ width then you can keep those GPIO advance PM configuration enable and don't need any override as Furquan has mentioned else better u set override_pm=1 and make bit4:0 all 0