[coreboot-gerrit] [M] Change in coreboot[main]: mb/google/{brya,hades}: use soc index for variant_update_power_limits()

[Subrata Banik (Code Review)]

Attention is currently required from: Dinesh Gehlot, Eric Lai, Kapil Porwal, Nick Vaccaro, SH Kim, Sumeet R Pawnikar.

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/81436?usp=email )

Change subject: mb/google/{brya,hades}: use soc index for variant_update_power_limits()
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Patch Set 5:

(1 comment)

File src/mainboard/google/brya/variants/baseboard/brya/ramstage.c:

https://review.coreboot.org/c/coreboot/+/81436/comment/0fc0c84f_e73cc8b5 :
PS5, Line 68: 			soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
> The override table has PL1/PL2 min/max values. I thought user might wish to override PL1/PL2 not only for MMIO register but MSR too, but I'm not sure about the original purpose of this code.
> Someone to confirm it to add override tdp_pl1_override and tdp_pl2_override here?

added Sumeet from Intel thermal side to commit (if any).